Abstract: A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when a second thread is generated from a first thread to be processed; determining whether the second thread operates exclusively from the first thread; copying a first storage area assessed by the first thread onto a second storage area managed by the CPU, when the second thread operates exclusively; calculating based on an address of the second storage area and a predetermined value, an offset for a second address for the second thread to access the first storage area; and notifying the CPU of the offset for the second address to convert a first address to a third address for accessing the second storage area.

Abstract: A multi-core system includes multiple processor cores; a bus connected to the processor cores; multiple peripheral devices accessed by the processor cores via the bus; profile information including information concerning access of the peripheral devices by each task assigned to the processor cores; a monitor that based on the profile information, monitors access requests to the peripheral devices from tasks under execution at the processor cores and prohibits an access request that causes contention at the bus; and a scheduler that when the monitor prohibits an access request that causes contention at the bus, switches to a different task.

Abstract: A data allocation method executed by a data allocation system. The data allocation method includes allocating to a first processing apparatus included among a plurality of processing apparatuses and allocating based on a first communication speed of the first processing apparatus, data having communication amount information on a frequency at which the processing apparatuses access the data, and further supplying first priority level information to the first processing apparatus; and exchanging based on variation of a communication speed of at least one processing apparatus among the processing apparatuses, the data or the first priority level information, and data or second priority level information allocated to a second processing apparatus included among the processing apparatuses and having a second communication speed.

Abstract: An interrupt monitoring apparatus includes a storage that stores a given threshold that corresponds to an external interrupt notification; a measuring circuit that measures time that elapses from a time when the external interrupt notification is received until a time when dispatch notification is received from a CPU; a comparing circuit that compares the given threshold and the time measured by the measuring circuit; and an output circuit that outputs to the CPU, a comparison result obtained by the comparing circuit.

Abstract: A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access.

Abstract: A processor management method includes setting a master mechanism in a given processor among multiple processors, where the master mechanism manages the processors; setting a local master mechanism and a virtual master mechanism in each of processors other than the given processor among the processors, where the local master mechanism and the virtual master mechanism manage each of the processors; and notifying by the master mechanism, the processors of an offset value of an address to allow a shared memory managed by the master mechanism to be accessed as a continuous memory by the processors.

Abstract: A distributed processing method of a system in which communications apparatuses communicate data by multi-hop communication is executed by a given communications apparatus among the communications apparatuses. According to the method, the given communications apparatus executes a given process based on a result of a first process executed by a first communications apparatus that among the communications apparatuses, communicates directly with the given communications apparatus and operates using power stored in a charging device charged by power generated from energy obtained corresponding to an environment where installed. The given communications apparatus executes the given process when receiving the result of the first process from the first communications apparatus.

Abstract: A multi-core processor system includes a given core among multiple cores, wherein the given core is configured to detect execution of a process by the cores; and generate upon detecting the execution of the process, a specific thread that saves state information indicating an executed state of the process and an executed state of each thread to be monitored of the process.

Abstract: A program executing method is executed by a computer and includes calculating a first power consumption for execution of a first program described by first code; calculating a second power consumption for execution of a second program of a function identical to that of the first program and described by second code; and converting the first program into the second program and executing the second program, if the second power consumption is less than the first power consumption.

Abstract: A communication method includes performing, by a processor, digital processing for radio communication by multiple communication schemes; combining based on an actual communication state and within a processing capability of the processor, one or more among the communication schemes; and performing concurrent communication.

Abstract: A data network management system includes a data network management apparatus; and plural data processing apparatuses installed in an installation area and configured to transmit data to the data network management apparatus. The plural data processing apparatuses transmit identification information thereof together with the processed data to the data network management apparatus. The data network management apparatus determines based on identification information of data processing apparatuses that have completed a given authentication test among the plural data processing apparatuses and the identification information obtained from the plural data processing apparatuses installed in the installation area, a first data processing apparatus from which the data is to be obtained among the plural data processing apparatuses.

Abstract: A multi-core processor system includes multiple cores and memory accessible from the cores, where a given core is configured to detect among the cores, first cores having a highest execution priority level; identify among the detected first cores, a second core that caused access conflict of the memory; and control a third core that is among the cores, excluding the first cores and the identified second core, the third core being controlled to execute for a given interval during an interval when the access conflict occurs, a thread that does not access the memory.

Abstract: A multi-core processor system includes a core configured to determine whether a task to be synchronized with a given task is present; identify among cores making up the multi-core processor and upon determining that a task to be synchronized with the given task is present, a core to which no non-synchronous task that is not synchronized with another task has been assigned, and identify among cores making up the multi-core processor and upon determining that a task to be synchronized with the given task is not present, a core to which no synchronous task to be synchronized with another task has been assigned; and send to the identified core, an instruction to start the given task.

Abstract: A communications node includes a first transmitting circuit configured to transmit to plural communications nodes, a confirmation signal for confirming whether response is possible; a receiving circuit configured to receive from first communications nodes capable of responding among the plural communications nodes, a response signal for the transmitted confirmation signal; a selecting circuit configured to select from among the first communications nodes and based on reception strength of the received response signal, a second communications node to which execution of data processing is requested by the communications node; a strength calculating circuit configured to calculate based on the reception strength of the response signal from the selected second communications node, a transmission strength to the second communications node; and a second transmitting circuit configured to transmit to the second communications node and based on the calculated transmission strength, a request signal requesting executi

Abstract: A communications method includes transmitting a sensor data collection request to a second network that includes a group of nodes having sensors, the transmitting being performed by a first communications apparatus of plural of communications apparatuses configured to communicate through a first network; and transmitting reception information to the first communications apparatus via the first network, when sensor data is received that is transferred by multihop communication among nodes in the second network and corresponds to the sensor data collection request, the reception information indicating reception of the sensor data, and the transmitting of the reception information being performed by a second communications apparatus of the plural communications apparatuses.

Abstract: A data processing apparatus includes a processor configured to receive an interrupt request that is a trigger for execution of an interrupt process executed by the processor; store the received interrupt request to a recording area; calculate based on a time when the interrupt request is received and particular time information read from the recording area, a predicted time when a subsequent interrupt request is to be received; detect a thread to be executed by the processor, among executable threads of the processor; judge based on the calculated predicted time and a current time, whether there is a possibility of the interrupt process being executed while the detected thread is under execution; decide based on a judgment result, whether to execute the detected thread on the processor; and execute the detected thread on the processor, based on a decision result.

Abstract: In an embodiment, a scheduler coordinates timings at which cores execute processes, for any two sequential processes to consecutively be executable. The processes are executed in order scheduled by the scheduler by concentrating on a specific core processes obstructing the consecutive execution such as an external interrupt and an internal interrupt. The scheduler does not always cause processes of another application to be executed during all standby time periods while the scheduler determines whether a length of a standby time period is shorter than a predetermined value, and does not cause any process of the other application to be executed when the length is shorter than that.

Abstract: A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

Abstract: A communication apparatus includes a first CPU that is capable of executing a communication process at a first processing speed; a measuring unit that measures a first transmission speed when the communication process is executed with a base station; a collecting unit that collects from at least one other apparatus, a second transmission speed between the base station and the apparatus, and a second processing speed of a second CPU included in the other apparatus based on the first transmission speed; a determining unit that determines whether the communication process is to be transferred to the other apparatus, based on the second transmission speed and the second processing speed; and a transferring unit that transfers the communication process to the other apparatus based on a determination result.

Abstract: A multicore processor system includes a processor configured to detect, among cores that have booted with an old boot program in the multicore processor, a core to which no process is assigned; change upon detecting a core to which no process is assigned, a reference area from a storage area for the old boot program to a storage area for a new boot program; and notify the core to which no process is assigned of a reboot instruction specifying the reference area after the change.