Abstract: A data collection method of a system that transmits and receives data by respective communications apparatuses among plural communications apparatuses performing multihop communication, includes suspending transmission of data obtained from a second sensor, a communications apparatus among the plural communications apparatuses suspending the transmission by the second communications apparatus when contents of data obtained from a first sensor of a first communications apparatus among the plural communications apparatuses and contents of data obtained from the second sensor of a second communications apparatus among the plural communications apparatuses are equivalent.

Abstract: A multicore processor system is configured to cause among multiple cores, a second core to acquire from a first core that executes a first process, an execution request for a second process and a remaining period from a time of execution of the execution request until an estimated time of completion of the first process; and give notification of a result of the second process from the second core to the first core after an estimated completion time of the first process obtained by adding the remaining period to a start time of the second process.

Abstract: A data sharing system includes communicable terminals and selects a server-client system in which a first terminal is designated as a server and other terminals are designated as clients, when a sum of estimated time for transferring data to the first terminal from the other terminals, estimated time for performing, by the first terminal, arithmetic processing of the data in the first terminal, and estimated time for transferring arithmetically processed data from the first terminal to the other terminals satisfies a real time restriction, and power estimated to be consumed at a time of performing, by the first terminal, the arithmetic processing of the data in the first terminal is less than power estimated to be consumed at a time of performing the arithmetic processing by the other terminals. The data sharing system selects a peer-to-peer system, when the sum does not satisfy the real time restriction in any terminal.

Abstract: A multicore system includes multiple processor cores; a scheduler in each of the processor cores and allocating a process to the processor cores when having a master authority that is an authority to assign processes; and a master controller performing control to repeat until a process to be executed no longer exists, a cycle in which the schedulers transfer the master authority to another processor core after receiving the master authority and before assigning a process to the processor cores, discards the master authority after assigning the process to the processor cores, and enters a state of waiting to receive the master authority.

Abstract: A computer-readable recording medium stores a control program causing a processor of a first terminal to execute a process that includes detecting that a remaining battery level of the first terminal has become less than or equal to a first threshold while a task is under execution by the first terminal; suspending execution of the task upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; transmitting identification information of the task to a second terminal upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; receiving from the second terminal and after transmitting the identification information of the task, information related to a potential of executing the task; and transmitting to the second terminal, information corresponding to the information related to the potential of executing the task.

Abstract: A data processing method executed by a first data processing apparatus and includes acquiring process information concerning a first process, in response to a process request for the first process; setting a first process flag included in the process information concerning the first process to indicate “true”; setting a first end flag of the process information concerning the first process to indicate “true” after executing the first process; acquiring process information concerning a second process that is to be executed before a third process that is to be executed subsequent the first process; and determining a process to be executed, based on a second process flag and a second end flag included in the process information concerning the second process.

Abstract: An assignment method executed by a given core of a multi-core processor includes identifying for each core, the number of storage areas to be used by a given thread and the number of storage areas used by threads already assigned; detecting for each core, a highest value from the number of storage areas used by the threads already assigned; determining whether a sum of a greater value of the detected highest value of a core selected as a candidate assignment destination and the number of storage areas to be used by the given thread, and the detected highest value of the cores excluding the selected core, is at most the number of storage areas of the shared resource; and assigning the given thread to the selected core, when the sum is at most the number of storage areas of the shared resource.

Abstract: A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process.

Abstract: A converting apparatus includes a storage configured to store correspondence information that indicates correspondence relations between logical addresses accessed by a processor for booting and physical addresses converted from the logical addresses, the correspondence information being correlated with each type of an event booting the processor; and an address converter configured to select correspondence information related to the type of the event, specify a physical address converted from the logical address accessed by the processor in case of the processor accessing a logical address in response to the event, and control the processor to get a program stored in the storage, the program indicated by the specified physical address.

Abstract: An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start of execution of a first application; starting measurement of an access time period, based on access of a peripheral device; outputting, when the access time period exceeds a predetermined time period, a detection signal to reset the driver; and prohibiting, when the access time period exceeds a predetermined time period, writing into a register retaining data to be written into the peripheral device from the first CPU.

Abstract: When a first sensor node has a large power consumption, an information processing apparatus propagates a portion of request information for a data process having the request recipient set to a second sensor node, through a path that does not pass through the first sensor node. For example, the information processing apparatus changes a division rate at a third sensor node acting as a branching point for the request information for the data process having the request recipient set to the second sensor node to thereby change the distribution of the transferred data amount and equalize the power consumption of the sensor nodes in a sensor network.

Abstract: A given sensor node, upon determining that data processing requested by another sensor node cannot be completed by the given sensor node, selects a sensor node that based on hop count based information stored in a storage apparatus, is away from a receiver. The given sensor node transmits to the selected sensor node, request notification requesting execution of the data processing exclusive of an executable portion. The given sensor node executes the executable portion, upon receiving securement completion notification indicating that the execution of the data processing indicated in the transmitted request notification can be completed by at least one sensor node among plural sensor nodes.

Abstract: A multicore processor system includes a core configured to detect a change in a state of assignment of a multicore processor; obtain, upon detecting the change in the state of assignment, number of accesses of a common resource shared by the multicore processor by each of process that are assigned to cores of the multicore processor; calculate an access ratio based on the obtained number of accesses; and notify an arbitration circuit of the calculated access ratio, the arbitration circuit arbitrating accesses of the common resource by the multicore processor.

Abstract: A computer obtains first information related to a first communication path that is from a first aggregating apparatus to a second aggregating apparatus when the second aggregating apparatus receives a transmission signal that is from sensor nodes in response to a transmission instruction that is transmitted by the first aggregating apparatus and propagated by multi-hop communication via the sensor nodes. The computer obtains from a storage apparatus, second information that is related to a second communication path that is a stationary path from the first aggregating apparatus to reception by the second aggregating apparatus. The computer determines correspondence of the first communication path and the second communication path by comparison of the first information and the second information, and if the first communication path and the second communication path do not correspond, the computer determines that an abnormality related to a sensor node is present.

Abstract: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.

Abstract: A multi-core processor system includes multiple cores; shared memory accessed by the cores; and an arbiter circuit that arbitrates contention of right to access the shared memory by the cores. Each of the cores is configured to acquire for the core, a measured speed of access to the shared memory; calculate for the core, a response performance based on the measured speed of access and a theoretical speed of access for the core; calculate for the cores and based on the response performance calculated for each of the cores, ratios of access rights to access the shared memory, the ratios being calculated such that a ratio of access rights for a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and notify the arbiter circuit of the calculated ratios of access rights.

Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.

Abstract: A converting apparatus includes a storage configured to store correspondence information that indicates correspondence relations between logical addresses accessed by a processor for booting and physical addresses converted from the logical addresses, the correspondence information being correlated with each type of an event booting the processor; and an address converter configured to select correspondence information related to the type of the event, specify a physical address converted from the logical address accessed by the processor in case of the processor accessing a logical address in response to the event, and control the processor to get a program stored in the storage, the program indicated by the specified physical address.

Abstract: A communications apparatus includes a receiving circuit that, when sending a startup instruction to start up another communications apparatus within a communication area, receives from the other communications apparatus, information indicating a period required for startup of the other communications apparatus; a processor that stores to a storage device, a standby period based on the period indicated by the information received by the receiving circuit; a communications circuit that sends the startup instruction within the communication area; and a timer that detects that the standby period stored in the storage device by the processor has elapsed after sending of the startup instruction from the communications circuit. The communications circuit sends data within the communication area when the timer detects that the standby period has elapsed.

Abstract: A multi-core processor system includes a core configured to detect that among cores different from a specific core executing a specific process, a given software different from specific software having a function equivalent to the specific process, is under execution; extract, from a database storing required computing capacities for the plural software and upon detecting that a given software is under execution, requirement values indicating the required computing capacity of the specific software and of the given software; judge for each the cores, whether a sum of the required computing capacities of the specific software and the software is at most a computing capacity value of the core; assign the specific software to a core for which the sum of the required computing capacities is judged to be at most the computing capacity value of the core; and suspend the specific core, upon assigning the specific software to the core.