Patents by Inventor Koichiro Yamashita

Koichiro Yamashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9098414
    Abstract: A multi-core processor system includes shared memory shared by cores of a multi-core processor; first cache memories respectively for each of the cores; a second cache memory between the shared memory and the first cache memories, and storing shared data shared by the cores and referred to by at least threads executed by the multi-core processor; a reading unit that reads a value of a given variable from the shared memory; a determining unit that based on a read request for the given variable, determines whether the given variable is shared data or non-shared data that is referred to by only one thread; and a transferring unit that, when the given variable is determined as non-shared data, transfers without using the second cache memory, the value of the given variable to a first cache memory of a core that is a request origin of the read request.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 4, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Patent number: 9099705
    Abstract: A fuel cell system includes: a fuel cell; a secondary cell that receives and stores surplus power by which output of the fuel cell is greater than power demanded of the system if the output is so, and that compensates for shortfall by which the output of the fuel cell is less than the power demanded of the system if the output is so; a voltage measurement portion that measures voltage of the fuel cell; a current measurement portion that measures current of the fuel cell; and a control portion that performs a control such that the voltage of the fuel cell does not exceed or equal a pre-set high-potential avoidance voltage. If a current-voltage characteristic of the fuel cell declines by at least a pre-determined amount from an early-period level, the control portion re-sets the high-potential avoidance voltage to a value that is smaller than an early-period set value.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: August 4, 2015
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Tomotaka Ishikawa, Hironori Noto, Keigo Suematsu, Koichiro Yamashita
  • Publication number: 20150211846
    Abstract: An event location analysis system includes a first wireless terminal device. The first wireless terminal device includes a first measurement unit, a second measurement unit, and a first processor. The second measurement unit consumes larger amounts of power than the first measurement unit consumes. The first processor is configured to transmit a first notification signal upon detecting a first event on basis of a measurement value of the first measurement unit. The first processor is configured to start the second measurement unit upon receiving a second notification signal. The first processor is configured to activate a measurement operation of the first measurement unit and a measurement operation of the second measurement unit after the second measurement unit is started. The first processor is configured to stop the measurement operation of the second measurement unit after a predetermined time has elapsed since the start of the second measurement unit.
    Type: Application
    Filed: November 21, 2014
    Publication date: July 30, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Takahisa SUZUKI, Koichiro Yamashita, Koji Kurihara, Toshiya Otomo
  • Patent number: 9092273
    Abstract: A multicore processor system includes a processor configured to detect any among a switching process and an assignment process of applications in a multicore processor; acquire upon detecting any among the switching process and the assignment process, a priority level concerning execution of each application assigned to each core of the multicore processor and number of accesses of a shared resource shared by the multicore processor; determine an access ratio of an application whose priority level is highest to each of application remaining after excluding the application whose priority level is highest, among the assigned applications, by comparing the number of accesses by each remaining application and the number of accesses by the application whose priority level is highest; notify an arbiter circuit of the determined access ratios; and arbitrate using the arbiter circuit, the access of the shared resource by the multicore processor, based on the access ratios.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 28, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Koji Kurihara, Koichiro Yamashita, Kiyoshi Miyazaki, Hitoshi Ikeda
  • Patent number: 9092255
    Abstract: A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: July 28, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Publication number: 20150203646
    Abstract: The method for producing the porous sheet of the present invention includes the steps of (I) preparing a plurality of sheet materials that contain polytetrafluoroethylene and carbon particles and (II) stacking the plurality of sheet materials over one another and rolling the stacked sheet materials. In the method for producing the porous sheet of the present invention, step (I) and step (II) may be repeated alternately. Further, as the sheet materials to be used in the production method of the present invention, a base sheet obtained by forming a mixture containing polytetrafluoroethylene and carbon particles into sheet form also can be used, or a laminated sheet obtained by stacking a plurality of base sheets over one another and rolling them also can be used, for example.
    Type: Application
    Filed: March 25, 2015
    Publication date: July 23, 2015
    Inventors: Takashi WANO, Hiroyuki HIGUCHI, Masayoshi KAWABE, Ryoichi MATSUSHIMA, Yoshinori YAMAMOTO, Koichiro YAMASHITA
  • Publication number: 20150201396
    Abstract: A communications apparatus is included among a communications apparatus group arranged in a given area and capable of communicating with a nearby communications apparatus. The communications apparatus includes a sensor that detects a given property at a location of the communications apparatus; communications circuitry that receives from the nearby communications apparatus, a detection result that is obtained by another communications apparatus, for the given property at the location of the other communications apparatus; a processor that determines whether a difference between the detection result received by the communications circuitry and a detection result of the sensor is a given amount or less.
    Type: Application
    Filed: March 26, 2015
    Publication date: July 16, 2015
    Applicant: Fujitsu Limited
    Inventors: Koichiro YAMASHITA, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo
  • Publication number: 20150201362
    Abstract: A communications apparatus includes a reception signal processor that receives a wireless signal; a processor that controls a wait time that the reception signal processor waits for reception of wireless signals that include data to be transmitted and information of transmission paths; extracts from the information of the transmission paths included in the wireless signals received by the reception signal processor during the wait time, information of a common relay point in the transmission paths; determines a network state according to a ratio of transmission paths that include the common relay point, among a total count of the transmission paths; and generates based on the determined network state, a signal that includes information of a relay point; and a transmission signal processor that transmits the generated signal.
    Type: Application
    Filed: March 25, 2015
    Publication date: July 16, 2015
    Applicant: Fujitsu Limited
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Toshiya Otomo
  • Publication number: 20150194198
    Abstract: A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution.
    Type: Application
    Filed: January 30, 2015
    Publication date: July 9, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Koichiro YAMASHITA, Fumihiko Hayakawa
  • Patent number: 9069756
    Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: June 30, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Hiromasa Yamauchi, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara
  • Publication number: 20150177361
    Abstract: A determining method includes obtaining by each monitoring apparatus among plural monitoring apparatuses disposed encompassing a given area having plural wireless communications apparatuses, hop count information that indicates a hop count of a wireless signal transmitted by one wireless communications apparatus among the wireless communications apparatuses and received by the monitoring apparatus via multi-hop communication by the wireless communications apparatuses; calculating by each monitoring apparatus, an estimated line that represents candidates of a position of the one wireless communications apparatus, the estimated line being calculated from an estimated distance between the monitoring apparatus and the one wireless communications apparatus, based on the hop count; correcting by each monitoring apparatus, the calculated estimated line based on information indicating a node-less area in which no wireless communications apparatus of the given area is present; and determining the position of the one w
    Type: Application
    Filed: March 3, 2015
    Publication date: June 25, 2015
    Applicant: Fujitsu Limited
    Inventors: Toshiya OTOMO, Koichiro Yamashita, Takahisa Suzuki, Hiromasa Yamauchi, Koji Kurihara, Yuta Teranishi
  • Publication number: 20150181528
    Abstract: A sensor node executes any one among a first operation by which another sensor node is requested to execute data process and if the request is not accepted the sensor node starts executing the data processing after waiting for charging and a second operation by which the sensor node starts executing the data processing after waiting for charging, without requesting the data processing to be executed. The sensor node compares an expected value of a first time that elapses until execution is started by the sensor node or the other sensor node when the first operation is executed, and a second time that elapses until execution is started by the sensor node when the second operation is executed. Based on the comparison result, the sensor node executes among the first operation and the second operation, the operation for which the time that elapses until execution is started is shorter.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 25, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Hiromasa YAMAUCHI, Koichiro Yamashita, Takahisa Suzuki, Koji Kurihara, Toshiya Otomo, Yuta Teranishi
  • Publication number: 20150169480
    Abstract: A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 18, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Hiromasa YAMAUCHI, Koichiro YAMASHITA, Takahisa SUZUKI, Koji KURIHARA
  • Publication number: 20150172791
    Abstract: A given communications apparatus is included among plural first communications apparatuses, among which at least execution results of data processing of the given communications apparatus is communicated by multi-hop communication whereby, the execution results are transmitted to a second communications apparatus that performs a process based on the execution results.
    Type: Application
    Filed: February 26, 2015
    Publication date: June 18, 2015
    Applicant: Fujitsu Limited
    Inventors: Hiromasa YAMAUCHI, Koichiro YAMASHITA, Takahisa SUZUKI, Koji KURIHARA, Toshiya OTOMO, Yuta TERANISHI
  • Publication number: 20150169456
    Abstract: A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present.
    Type: Application
    Filed: February 24, 2015
    Publication date: June 18, 2015
    Inventors: Takahisa SUZUKI, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Patent number: 9052993
    Abstract: A multi-core processor system includes a memory unit that for each input destination thread defined as a thread to which given data is input, stores identification information of an assignment destination core for the input destination thread; and a multi-core processor that is configured to update, in the memory unit and when assignment of the input destination thread to a multi-core processor is detected, the identification information of the assignment destination core for the input destination thread; detect a writing request for the given data; identify based on the given data for which the writing request is detected, the updated identification information among information stored in the memory unit; and store the given data to a memory of the assignment destination core that is indicated in the updated identification information and among cores making up the multi-core processor.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: June 9, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Takahisa Suzuki, Koichiro Yamashita, Hiromasa Yamauchi, Koji Kurihara
  • Publication number: 20150153439
    Abstract: A determining method executed by a processor includes obtaining distance information that indicates a distance between monitoring apparatuses disposed to encompass a given area in which wireless communications apparatuses are scattered; causing a wireless signal to be transmitted and received between the monitoring apparatuses by multi-hop communication among the wireless communications apparatuses; calculating an estimated distance between the monitoring apparatuses, based on a hop count of the wireless signal multi-hop communicated among the monitoring apparatuses; and making a determination concerning a vacant area in which none of the wireless communications apparatuses is present, based on a result of comparison of the distance indicated by the obtained distance information and the calculated estimated distance.
    Type: Application
    Filed: February 11, 2015
    Publication date: June 4, 2015
    Applicant: Fujitsu Limited
    Inventors: Toshiya OTOMO, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Koji KURIHARA, Yuta TERANISHI
  • Patent number: 9043520
    Abstract: In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 26, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara
  • Patent number: 9043507
    Abstract: An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: May 26, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Koichiro Yamashita, Hiromasa Yamauchi, Takahisa Suzuki, Koji Kurihara, Fumihiko Hayakawa
  • Publication number: 20150137995
    Abstract: A sensor node detects an occurrence of sensing and judges whether data processing corresponding to the sensing will finish before an occurrence of sensing subsequent to the sensing, based on a time interval when the occurrence of the sensing is detected. When determining that the data processing will finish, the sensor node executes the data processing and transmits the execution result of the data processing to a first apparatus directly communicable with the sensor node. When determining that the data processing will not finish, the sensor node transmits, to the first apparatus, request information causing the first apparatus to execute the data processing and to transmit the execution result of the data processing to a second communication apparatus directly communicable with the first apparatus.
    Type: Application
    Filed: January 23, 2015
    Publication date: May 21, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Koji KURIHARA, Koichiro YAMASHITA, Takahisa SUZUKI, Hiromasa YAMAUCHI, Toshiya OTOMO, Yuta TERANISHI