Abstract: A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: This invention computerizes work requiring a “determination” that reflects all requests for each of a plurality of determination materials. A table 011 that associates “a combination of determination grounds information” and “determination result information” is formed by making use of: the fact that determination result information is information of a limited scope according to the purpose and the content of determination work; and the fact that a feature, performance, price, application or the like included in the determination result information, which serve as “grounds” for making a determination, are used as a “combination of determination grounds information”, which makes it possible to identify the determination result information.

Abstract: Provided is a method for producing a lithium tantalate single crystal substrate capable of suppressing increase in volume resistivity of the lithium tantalate single crystal substrate owing to reduction failure even when a lithium carbonate power is repeatedly used in heat treatment for the lithium tantalate single crystal substrate. The invention is a method for producing a lithium tantalate single crystal substrate having a volume resistivity of 1×1010 ?·cm or more and less than 1×1012 ?·cm, including a step of heat-treating a lithium tantalate single crystal substrate having a volume resistivity of 1×1012 ?·cm or more and having a single-domain structure, under normal pressure and at a temperature of 350° C. or higher but not higher than the Curie temperature thereof while burying it in a lithium carbonate powder having a BET specific surface area of 0.

Abstract: A semiconductor memory device comprises: a substrate; a first conductive layer separated from the substrate in a first direction and extending in a second direction; a second and a third conductive layers separated from the substrate and the first conductive layer in the first direction and aligned in the second direction; a first semiconductor layer facing the first and the second conductive layers; a second semiconductor layer facing the first and the third conductive layers; a first and a second bit lines electrically connected to the first and the second semiconductor layers. At least some of operation parameters in the case of a certain operation being executed on a memory cell corresponding to the first conductive layer differ from at least some of operation parameters in the case of the certain operation being executed on a memory cell corresponding to the second conductive layer or the third conductive layer.

Abstract: A semiconductor memory device includes: conductive layers including a first range and a second range; a first semiconductor layer opposed to the conductive layers in the first range; a second semiconductor layer opposed to the conductive layers in the second range; a first bit line electrically connected to one end of the first semiconductor layer; and a second bit line electrically connected to one end of the second semiconductor layer. When a sense time of the first bit line when a predetermined operation is performed on a first memory cell including a first electric charge accumulating portion is assumed to be a first operation parameter and a sense time of the second bit line when the predetermined operation is performed on a second memory cell including a second electric charge accumulating portion is assumed to be a second operation parameter, the second operation parameter differs from the first operation parameter.

Abstract: A wire harness manufacturing system including a plurality of processing zones and configured to manufacture a wire harness by using a subassembly including a plurality of electrical lines to each of which a connection component is attached includes a conveyance device provided along the plurality of processing zones and including: work boards in a number at least corresponding to the number of the plurality of processing zones; a circulation conveyer configured to sequentially convey each work board in a horizontal state from an upstream side to a downstream side on a downstream conveyance path along the plurality of processing zones and then return the work board from the downstream side to the upstream side on an upstream conveyance path; and a raiser configured to set the work board to a stand-up state in which one of edge parts extending in a conveyance direction of the work board is positioned on an upper side of the other edge part in the work board, and to set the work board in the stand-up state to th

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: A sulfide solid electrolyte, which is able to adjust the morphology unavailable traditionally, or is readily adjusted so as to have a desired morphology, the sulfide solid electrolyte having a volume-based average particle diameter measured by laser diffraction particle size distribution measurement of 3 ?m or more and a specific surface area measured by the BET method of 20 m2/g or more; and a method of treating a sulfide solid electrolyte including the sulfide solid electrolyte being subjected to at least one mechanical treatment selected from disintegration and granulation.

Abstract: A method and system for provisioning a first computing device and authenticating the provisioned first computing device are disclosed, comprising sending a request to prepare the first computing device, including providing a request identifier and an authentication token to be stored on the provisioned first computing device, receiving a unique identifier of the provisioned first computing device, storing the request identifier, the authentication token, and the received unique identifier in a provisioning data structure, and authenticating the provisioned first computing device on the network based on a determination that a unique identifier and the authentication token stored on the provisioned first computing device requesting authentication match both the authentication token and the received unique identifier of the provisioned first computing device in the provisioning data structure.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A sulfide solid electrolyte, which is able to adjust the morphology unavailable traditionally, or is readily adjusted so as to have a desired morphology, the sulfide solid electrolyte having a volume-based average particle diameter measured by laser diffraction particle size distribution measurement of 3 ?m or more and a specific surface area measured by the BET method of 20 m2/g or more; and a method of treating a sulfide solid electrolyte including the sulfide solid electrolyte being subjected to at least one mechanical treatment selected from disintegration and granulation.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A method and system for automatic device provisioning includes a computer system for authenticating a user using a first device. The computer system receives a request for automatic provisioning of a second device. An authentication token and a request identifier of the request is associated with a provisioning data structure for the user. The request including the authentication token is sent to a third device. The computer system receives a unique identifier for the second device from the third device. Based on a determination that the unique identifier and the authentication token of the second device match the unique identifier and authentication token in the provisioning data structure, authenticate the second device, retrieve a configuration profile for the user, and cause application of the configuration profile to one or more settings of the second device.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A method and system for automatic device provisioning includes a computer system for authenticating a user using a first device. The computer system receives a request for automatic provisioning of a second device. An authentication token and a request identifier of the request is associated with a provisioning data structure for the user. The request including the authentication token is sent to a third device. The computer system receives a unique identifier for the second device from the third device. Based on a determination that the unique identifier and the authentication token of the second device match the unique identifier and authentication token in the provisioning data structure, authenticate the second device, retrieve a configuration profile for the user, and cause application of the configuration profile to one or more settings of the second device.

Abstract: A semiconductor memory device includes a memory string, first wirings electrically connected to the memory string, second wirings electrically connected to the first wirings, transistors electrically connected between the first wirings and the second wirings, and a third wiring connected to gate electrodes of the transistors in common. The memory string includes memory transistors connected in series. Gate electrodes of the memory transistors are connected to the first wirings. The semiconductor memory device executes a first read operation in response to an input of a first command set, and executes a second read operation in response to an input of a second command set. A first voltage that turns the transistors ON is applied to the third wiring from an end of the first read operation to a start of the second read operation.

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.