Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

Abstract: A semiconductor memory device according to an embodiment includes memory cell transistors, a word line, and a controller. A memory cell transistor whose threshold voltage is included in first and second states store first and second data, respectively. In a verify operation of the first data, during application of a verify high voltage of the first data to the word line, the controller is configured to determine whether or not a threshold voltage of a memory cell transistor to which the first data is to be written exceeds the verify high voltage of the first data, and also determine whether or not a threshold voltage of a memory cell transistor to which the second data is to be written exceeds a verify low voltage of the second data.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: Provided is a method for producing a lithium tantalate single crystal substrate capable of suppressing increase in volume resistivity of the lithium tantalate single crystal substrate owing to reduction failure even when a lithium carbonate power is repeatedly used in heat treatment for the lithium tantalate single crystal substrate. The invention is a method for producing a lithium tantalate single crystal substrate having a volume resistivity of 1×1010 ?·cm or more and less than 1×1012 ?·cm, including a step of heat-treating a lithium tantalate single crystal substrate having a volume resistivity of 1×1012 ?·cm or more and having a single-domain structure, under normal pressure and at a temperature of 350° C. or higher but not higher than the Curie temperature thereof while burying it in a lithium carbonate powder having a BET specific surface area of 0.

Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A semiconductor storage device includes a plurality of memory cells connected to each other in series, a plurality of word lines respectively connected to gates of the plurality of memory cells, and a control circuit configured to perform a read operation by applying a first voltage higher than ground voltage to the plurality of word lines during a first time period at the beginning of which each word line is at ground voltage, applying a second voltage lower than the first voltage to a first word line during a second time period subsequent to the first time period, applying a third voltage higher than the second voltage to the first word line during a third time period subsequent to the second time period, and determining data of the memory cells connected to the first word line while all portions of the first word line are at the third voltage.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: An image forming apparatus includes: a cover; a power supply that supplies a drive system supply voltage and a control system supply voltage in an operating mode, and that supplies the control system supply voltage without supplying the drive system supply voltage in a power saving mode; an interlock switch including a first terminal that receives the drive system supply voltage, a second terminal that receives the control system supply voltage, and a third terminal connected to a line for supplying the drive system supply voltage to an image forming portion, the interlock switch connecting the first and third terminals when the cover is closed, and connecting the second and third terminals when the cover is open; and a detector that, when the control system supply voltage is applied to the line in the power saving mode, stores information indicating that the cover has been opened.

Abstract: A semiconductor memory device includes a block decoder having a sense node, and a control unit. The block decoder includes first and second transistors each connected between a first node and ground, a third transistor connected between a power source voltage and a second node, a fourth transistor connected between the first and second nodes and controlled by the same gate signal as the third transistor, a fifth transistor having a first terminal connected to the sense node and a gate connected to the second node through an inverter, and a latch circuit that switches the first transistor on and off according to its setting. The control unit determines the setting of the latch circuit, according to a logic level based on a voltage of the sense node during an operation in which the second and third transistors are turned off and the fourth transistor is turned on.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: To provide a method for producing a composite wafer capable of reducing a spurious arising by reflection of an incident signal on a joint interface between a lithium tantalate film and a supporting substrate, in the composite wafer including a supporting substrate having a low coefficient of thermal expansion, and a lithium tantalate film having a high coefficient of thermal expansion stacked on the supporting substrate. The method for producing a composite wafer is a method for producing a composite wafer that produces a composite wafer by bonding a lithium tantalate wafer having a high coefficient of thermal expansion to a supporting wafer having a low coefficient of thermal expansion, wherein prior to bonding together, ions are implanted from a bonding surface of the lithium tantalate wafer and/or the supporting wafer, to disturb crystallinity near the respective bonding surfaces.

Abstract: An image forming apparatus includes: a cover; a power supply that supplies a drive system supply voltage and a control system supply voltage in an operating mode, and that supplies the control system supply voltage without supplying the drive system supply voltage in a power saving mode; an interlock switch including a first terminal that receives the drive system supply voltage, a second terminal that receives the control system supply voltage, and a third terminal connected to a line for supplying the drive system supply voltage to an image forming portion, the interlock switch connecting the first and third terminals when the cover is closed, and connecting the second and third terminals when the cover is open; and a detector that, when the control system supply voltage is applied to the line in the power saving mode, stores information indicating that the cover has been opened.

Abstract: A sulfide solid electrolyte, which is able to adjust the morphology unavailable traditionally, or is readily adjusted so as to have a desired morphology, the sulfide solid electrolyte having a volume-based average particle diameter measured by laser diffraction particle size distribution measurement of 3 ?m or more and a specific surface area measured by the BET method of 20 m2/g or more; and a method of treating a sulfide solid electrolyte including the sulfide solid electrolyte being subjected to at least one mechanical treatment selected from disintegration and granulation.

Abstract: An object of the present invention is to provide a bonded substrate which is excellent in temperature characteristics and suppresses unnecessary response due to reflection of an elastic wave at a bonding interface. [Means to Solve the Problems] The present invention is unique in that a bonded substrate is constructed by bonding a LiTaO3 substrate and a base plate wherein a Li concentration at a base plate-bonding face of the LiTaO3 substrate is higher than that at a LiTaO3 substrate-side end face of the bonded substrate, that the difference between the Li concentration at the base plate-bonding face of the LiTaO3 substrate and the Li concentration at the LiTaO3 substrate-side end face of the bonded substrate is 0.1 mol % or greater, that the Li concentration at the base plate-bonding face of the LiTaO3 substrate satisfies an equation Li/(Li+Ta)×100=(50+?) mol %, where ? is in the range of ?1.2<?<0.

Abstract: [Object] It is an object of the present invention to provide a lithium tantalate single crystal substrate which undergoes only small warpage, is free from cracks and scratches, has better temperature non-dependence characteristics and a larger electromechanical coupling coefficient than a conventional Y-cut LiTaO3 substrate.

Abstract: A wire harness manufacturing system including a plurality of processing zones and configured to manufacture a wire harness by using a subassembly including a plurality of electrical lines to each of which a connection component is attached includes a conveyance device provided along the plurality of processing zones and including: work boards in a number at least corresponding to the number of the plurality of processing zones; a circulation conveyer configured to sequentially convey each work board in a horizontal state from an upstream side to a downstream side on a downstream conveyance path along the plurality of processing zones and then return the work board from the downstream side to the upstream side on an upstream conveyance path; and a raiser configured to set the work board to a stand-up state in which one of edge parts extending in a conveyance direction of the work board is positioned on an upper side of the other edge part in the work board, and to set the work board in the stand-up state to th

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.