Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A rotating electric machine includes a case, a stator, a first rotary member including a rotor core and a first shaft, a second rotary member including a second shaft, and a multiple disc clutch. A first oil passage and a second oil passage are provided inside the case. The first oil passage starts from an inside of the first shaft or an inside of the second shaft, passes through the multiple disc clutch from an inner side to an outer side in a radial direction with respect to a rotation center, and reaches an inner side of the rotor core in the radial direction. The second oil passage starts from the inside of the first shaft or the inside of the second shaft and reaches the inner side of the rotor core in the radial direction without passing through the multiple disc clutch.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A semiconductor storage device includes a plurality of memory cells connected to each other in series, a plurality of word lines respectively connected to gates of the plurality of memory cells, and a control circuit configured to perform a read operation by applying a first voltage higher than ground voltage to the plurality of word lines during a first time period at the beginning of which each word line is at ground voltage, applying a second voltage lower than the first voltage to a first word line during a second time period subsequent to the first time period, applying a third voltage higher than the second voltage to the first word line during a third time period subsequent to the second time period, and determining data of the memory cells connected to the first word line while all portions of the first word line are at the third voltage.

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

Abstract: A vehicle body floor structure has: a floor panel having a side edge; a side sill joined to the side edge of the floor panel; a cross member connected to the side sill, the cross member extending in a direction that crosses a direction in which the side sill extends; a first reinforcing member disposed at an internal corner defined by the side sill and the cross member, the first reinforcing member joined to the side sill and to a joint portion of the cross member; and a second reinforcing member disposed at the joint portion of the cross member. The first reinforcing member has an end portion located on a side of the joint portion and having a weak portion.

Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

Abstract: A method is provided for predicting the therapeutic effectiveness of chemotherapy for a diffuse large B-cell lymphoma patient, including: at least one step selected from the group consisting of a step of measuring expression of a marker of a T cell in a sample obtained from the patient, a step of measuring expression of a marker of a macrophage or a dendritic cell in a sample obtained from the patient, and a step of measuring expression of a marker of a stromal cell in a sample obtained from the patient; and a step of predicting prognosis of the treatment, based on the expression of the marker.

Abstract: An object of the present invention is to provide a method of manufacturing a composite substrate including a piezoelectric layer with less Li amount variation and a support substrate. A method of manufacturing a composite substrate of the present invention includes a step of performing ion implantation into a piezoelectric substrate, a step of bonding the piezoelectric substrate and the support substrate, a step of separating the bonded substrate, at an ion-implanted portion of the piezoelectric substrate, into the piezoelectric layer bonded to the support substrate and the remaining piezoelectric substrate after the step of bonding the piezoelectric substrate and the support substrate, and a step of diffusing Li into the piezoelectric layer after the separating step.

Abstract: A semiconductor memory device includes a block decoder having a sense node, and a control unit. The block decoder includes first and second transistors each connected between a first node and ground, a third transistor connected between a power source voltage and a second node, a fourth transistor connected between the first and second nodes and controlled by the same gate signal as the third transistor, a fifth transistor having a first terminal connected to the sense node and a gate connected to the second node through an inverter, and a latch circuit that switches the first transistor on and off according to its setting. The control unit determines the setting of the latch circuit, according to a logic level based on a voltage of the sense node during an operation in which the second and third transistors are turned off and the fourth transistor is turned on.

Abstract: A semiconductor memory device includes a block decoder having a sense node, and a control unit. The block decoder includes first and second transistors each connected between a first node and ground, a third transistor connected between a power source voltage and a second node, a fourth transistor connected between the first and second nodes and controlled by the same gate signal as the third transistor, a fifth transistor having a first terminal connected to the sense node and a gate connected to the second node through an inverter, and a latch circuit that switches the first transistor on and off according to its setting. The control unit determines the setting of the latch circuit, according to a logic level based on a voltage of the sense node during an operation in which the second and third transistors are turned off and the fourth transistor is turned on.

Abstract: An object of the present invention is to provide a method of manufacturing a composite substrate including a piezoelectric layer with less Li amount variation and a support substrate. A method of manufacturing a composite substrate of the present invention includes a step of performing ion implantation into a piezoelectric substrate, a step of bonding the piezoelectric substrate and the support substrate, a step of separating the bonded substrate, at an ion-implanted portion of the piezoelectric substrate, into the piezoelectric layer bonded to the support substrate and the remaining piezoelectric substrate after the step of bonding the piezoelectric substrate and the support substrate, and a step of diffusing Li into the piezoelectric layer after the separating step.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A semiconductor memory device comprises a first memory cell array including a first memory cell and a second memory cell array including a second memory cell, a first transistor electrically connectable to a first end of the first memory cell via a first source line, a second transistor connectable to a first end of the second memory cell via a second source line, a pad supplied with a reference voltage from outside, a first wiring that electrically connects the first transistor and the pad, and a second wiring that is different from the first wiring and electrically connects the second transistor and the pad.

Abstract: A rotating electric machine includes a case, a stator, a first rotary member including a rotor core and a first shaft, a second rotary member including a second shaft, and a multiple disc clutch. A first oil passage and a second oil passage are provided inside the case. The first oil passage starts from an inside of the first shaft or an inside of the second shaft, passes through the multiple disc clutch from an inner side to an outer side in a radial direction with respect to a rotation center, and reaches an inner side of the rotor core in the radial direction. The second oil passage starts from the inside of the first shaft or the inside of the second shaft and reaches the inner side of the rotor core in the radial direction without passing through the multiple disc clutch.

Abstract: A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: A vehicle body floor structure has: a floor panel having a side edge; a side sill joined to the side edge of the floor panel; a cross member connected to the side sill, the cross member extending in a direction that crosses a direction in which the side sill extends; a first reinforcing member disposed at an internal corner defined by the side sill and the cross member, the first reinforcing member joined to the side sill and to a joint portion of the cross member; and a second reinforcing member disposed at the joint portion of the cross member. The first reinforcing member has an end portion located on a side of the joint portion and having a weak portion.