Abstract: A semiconductor memory device includes a block decoder having a sense node, and a control unit. The block decoder includes first and second transistors each connected between a first node and ground, a third transistor connected between a power source voltage and a second node, a fourth transistor connected between the first and second nodes and controlled by the same gate signal as the third transistor, a fifth transistor having a first terminal connected to the sense node and a gate connected to the second node through an inverter, and a latch circuit that switches the first transistor on and off according to its setting. The control unit determines the setting of the latch circuit, according to a logic level based on a voltage of the sense node during an operation in which the second and third transistors are turned off and the fourth transistor is turned on.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: To provide a method for producing a composite wafer capable of reducing a spurious arising by reflection of an incident signal on a joint interface between a lithium tantalate film and a supporting substrate, in the composite wafer including a supporting substrate having a low coefficient of thermal expansion, and a lithium tantalate film having a high coefficient of thermal expansion stacked on the supporting substrate. The method for producing a composite wafer is a method for producing a composite wafer that produces a composite wafer by bonding a lithium tantalate wafer having a high coefficient of thermal expansion to a supporting wafer having a low coefficient of thermal expansion, wherein prior to bonding together, ions are implanted from a bonding surface of the lithium tantalate wafer and/or the supporting wafer, to disturb crystallinity near the respective bonding surfaces.

Abstract: [Object] An object of the present invention is to provide a bonded substrate which is excellent in temperature characteristics and suppresses unnecessary response due to reflection of an elastic wave at a bonding interface. [Means to Solve the Problems] The present invention is unique in that a bonded substrate is constructed by bonding a LiTaO3 substrate and a base plate wherein a Li concentration at a base plate-bonding face of the LiTaO3 substrate is higher than that at a LiTaO3 substrate-side end face of the bonded substrate, that the difference between the Li concentration at the base plate-bonding face of the LiTaO3 substrate and the Li concentration at the LiTaO3 substrate-side end face of the bonded substrate is 0.1 mol % or greater, that the Li concentration at the base plate-bonding face of the LiTaO3 substrate satisfies an equation Li/(Li+Ta)×100=(50+?) mol %, where ? is in the range of ?1.2<?<0.

Abstract: According to one embodiment, a memory device includes a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first word line connected to the first memory cell and the second memory cell; a first circuit configured to control a connection between the first bit line and a first node; and a second circuit configured to control a connection between the second bit line and the first node.

Abstract: A semiconductor memory device includes a plurality of blocks of memory cells, including first, second, and third blocks of a first group of blocks and fourth fifth and sixth blocks of a second group of blocks, a plurality of word lines for each of the blocks, a first decode circuit for the first group, and a second decode circuit for the second group. When the first block is selected, the first decode circuit transfers a first voltage to the word lines of the first block, transfers a second voltage lower than the first voltage to the word lines of the second block, and causes the word lines of the third block to go into an electrically floating state, and the second decode circuit causes the words lines of the fourth block, the fifth block, and the sixth block into the electrically floating state.

Abstract: A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.

Abstract: According to one embodiment, a semiconductor memory device includes a row decoder that outputs a first signal to a first wiring and outputs a second signal to a second wiring, a switch that has one end to which a first voltage is supplied, another end connected to the first wiring, and a gate connected to the second wiring, a first transistor and a second transistor that have respective gates connected to the first wiring at connecting positions located between the row decoder and the another end of the switch on the first wiring, a third transistor and a fourth transistor that have respective gates to which signals having opposite logic levels are respectively input, and a driver that is connected to one end of the first transistor via the third transistor and is connected to one end of the second transistor via the fourth transistor.

Abstract: A semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier electrically connected to the bit line and including a first latch, and a controller configured to execute a write operation on the memory cell. The write operation includes a first program operation followed by a verify operation that includes a step of updating data of the first latch and a second program operation that includes a step of pre-charging the bit line, wherein the step of pre-charging the bit line is initiated prior to the data of the first latch is updated.

Abstract: Provided is a capacitive touch switch panel on which it is possible to form a transparent sensor electrode having high quality design shape and reduced reflection of visible light, and which moreover has excellent appearance and ample environmental resistance. This capacitive touch switch panel 1 is provided with a glass substrate 2, and with a sensor part 3 formed on this glass substrate 2. The sensor part 3 has a sensor electrode 4, this sensor electrode 4 comprising an Al thin film formed by sputtering or vacuum deposition into a switch configuration on the glass substrate 2 at the opposite surface side 2b from a touch surface 2a, the sensor part 3 having an intermediate layer between the glass substrate 2 and at least a portion of the Al thin film. This intermediate layer comprises a thin film that includes at least one metal selected from Cr, Mo, and W.

Abstract: [Object] It is an object of the present invention to provide a lithium tantalate single crystal substrate which undergoes only small warpage, is free from cracks and scratches, has better temperature non-dependence characteristics and a larger electromechanical coupling coefficient than a conventional Y-cut LiTaO3 substrate.

Abstract: A semiconductor memory device includes a memory cell, a bit line electrically connected to the memory cell, a sense amplifier electrically connected to the bit line and including a first latch, and a controller configured to execute a write operation on the memory cell. The write operation includes a first program operation followed by a verify operation that includes a step of updating data of the first latch and a second program operation that includes a step of pre-charging the bit line, wherein the step of pre-charging the bit line is initiated prior to the data of the first latch is updated.

Abstract: The lithium tantalate single crystal substrate is a rotated Y-cut LiTaO3 single crystal substrate having a crystal orientation of 36° Y-49° Y cut characterized in that: the substrate is diffused with Li from its surface into its depth such that it has a Li concentration profile showing a difference in the Li concentration between the substrate surface and the depth of the substrate; and the substrate is treated with single polarization treatment so that the Li concentration is substantially uniform from the substrate surface to a depth which is equivalent to 5-15 times the wavelength of either a surface acoustic wave or a leaky surface acoustic wave propagating in the LiTaO3 substrate surface.

Abstract: A PBN-coated carbon heater is disclosed in which the carbon base body is anisotropic with respect to thermal expansion coefficient such that the maximum-to-minimum coefficient ratio is 1.02 through 1.50 for temperatures between 50 and 800 degree C.; preferably the carbon base body is also anisotropic with respect to electric resistivity such that the maximum-to-minimum resistivity ratio is greater than 1.04 but not greater than 1.51, and the direction in which the resistivity is maximum coincides the direction of the heater pattern in which the electricity runs the longest distance.

Abstract: According to one embodiment, a semiconductor memory device includes a row decoder that outputs a first signal to a first wiring and outputs a second signal to a second wiring, a switch that has one end to which a first voltage is supplied, another end connected to the first wiring, and a gate connected to the second wiring, a first transistor and a second transistor that have respective gates connected to the first wiring at connecting positions located between the row decoder and the another end of the switch on the first wiring, a third transistor and a fourth transistor that have respective gates to which signals having opposite logic levels are respectively input, and a driver that is connected to one end of the first transistor via the third transistor and is connected to one end of the second transistor via the fourth transistor.

Abstract: A laminate from which containers with improved transparency, high low-temperature impact strength and rigidity can be made. The laminate includes a resin layer [I] containing 60.0% by mass or more and 85.0% by mass or less of a propylene-based polymer (A) and 15.0% by mass or more and 40.0% by mass or less of an ethylene-based polymer (B), and a resin layer [II] containing 80.0% by mass or more and 99.9% by mass or less of a propylene-based polymer (A), 0.0% by mass or more and less than 15.0% by mass of an ethylene-based polymer (B), and 0.1% by mass or more and 20.0% by mass or less of a nucleating agent (C). The propylene-based polymer (A) and the ethylene-based polymer (B) satisfy specific requirements in both of the resin compositions [I] and [II].

Abstract: A medium carrying device includes a carrying part that carries a continuous print medium, a detection part that includes a light emitting part and a light receiving part arranged sandwiching a carrying path, and that detects the print medium carried on the carrying path according to a light amount that is received by the light receiving part, and a control part that controls operations of the carrying part and the detection part, wherein the control part sets a first emitted light amount of the emitted light of the light emitting part used in image formation to the print medium by performing a light amount measurement using the light emitting part and the light receiving part in a state where the print medium is carried to a first position, and sets a threshold light amount that is used in detecting a boundary position between the first region and the second region by the detection part through performing another light amount measurement by obtaining a receiving light amount of the light receiving part with t

Abstract: A cooling structure of a rotary electric machine (10) that includes a rotating shaft (16), a rotor (18), and a stator (20) that includes a coil end (22), includes a coolant passage (38) that is included in the rotating shaft (16) and through which coolant flows, and a squirt hole (42) that is included in the coolant passage (38). The squirt hole (42) is included in the coolant passage (38). An opening portion of the squirt hole (42) is positioned on an outer peripheral surface of the rotating shaft (16) and to an outside of the coil end (22) in the axial direction. The squirt hole (42) squirts the coolant such that the coolant is distributed to an inner peripheral surface (C1, C2) of the coil end (22) and an end surface (A1, A2) of the coil end (22) in the axial direction.

Abstract: According to one embodiment, a memory device includes a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first word line connected to the first memory cell and the second memory cell; a first circuit configured to control a connection between the first bit line and a first node; and a second circuit configured to control a connection between the second bit line and the first node.

Abstract: According to one embodiment, a memory device includes a string unit including a plurality of memory cell transistors which are connected in series, a first select transistor connected to a first end of the plurality of memory cell transistors, and a second select transistor connected to a second end of the plurality of memory cell transistors; and a bit line connected to the first select transistor.