Patents by Inventor Koki Ueno
Koki Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130044544Abstract: According to one embodiment, a nonvolatile memory device includes a circuit and a memory cell. The circuit outputs a program voltage. The memory cell is programmed data by being applied the program voltage. The circuit outputs the program voltage so as to satisfy the following formulae, in the case of repeating an output of the program voltage n times (n is an integer not less than 3), when the program voltage in the k-th output (k is an integer not less than 2 and not greater than n) is set to Vpgm(k), a constant voltage is set as ?v1, a time in which the k-th output is continued is set to Tpgm(k), and a constant time is set as ?t1.Type: ApplicationFiled: March 6, 2012Publication date: February 21, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiro SHIINO, Manabu SAKANIWA, Shigefumi IRIEDA, Koki UENO
-
Publication number: 20130024079Abstract: Disclosed is a shift range switching apparatus of an automatic transmission which can improve the durability over the conventional shift range switching apparatus. An ECU is operative to rotate an actuator in a predetermined direction (Step S2) in the state of the automatic transmission switched to a predetermined shift range (Step S1), and thereafter the actuator is deenergized (Step S3). The reference position of the actuator corresponding to the predetermined shift range is detected (Step S5) in accordance with the fluctuation of the count value counted by an encoder when the actuator is deenergized (Step S4).Type: ApplicationFiled: April 15, 2010Publication date: January 24, 2013Inventors: Keisuke Sekiya, Koki Ueno, Mitsuaki Ishimaru
-
Publication number: 20130000436Abstract: An HV-ECU executes a program including a step (S102) of turning on a fail-safe permission flag if a select sensor is abnormal (YES in step S100), and a step (S108) of transmitting a non-P request signal to a P-ECU if the position of a shift lever is read as the N position (YES in S104) and a predetermined time Tn(2) elapses (YES in S106).Type: ApplicationFiled: September 11, 2012Publication date: January 3, 2013Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Koki UENO
-
Publication number: 20130003454Abstract: A non-volatile semiconductor memory device according to embodiments has a memory cell array and a reading circuit, and, in a reading sequence, the reading circuit executes a prereading operation of supplying a first reading voltage to an adjacent word line and supplying a first reading pass voltage to a selected word line, and after executing the prereading operation, executes a main reading operation of supplying a fixed second reading voltage to the selected word line and supplying a fixed second reading pass voltage to the adjacent word line while sensing a plurality of electrical physical amounts of a target memory cell with different reading conditions.Type: ApplicationFiled: June 29, 2012Publication date: January 3, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshiaki Edahiro, Masahiro Noguchi, Koki Ueno
-
Patent number: 8335619Abstract: An HV-ECU executes a program including a step of turning on a fail-safe permission flag if a select sensor is abnormal, and a step of transmitting a non-P request signal to a P-ECU if the position of a shift lever is read as the N position and a predetermined time Tn elapses.Type: GrantFiled: May 23, 2008Date of Patent: December 18, 2012Assignee: Toyota Jidosha Kabushiki KaishaInventor: Koki Ueno
-
Publication number: 20120305360Abstract: It is provided a shift control device for a vehicle having a parking lock device driven by an actuator to selectively switch switching positions between a lock position and an unlock position, wherein when a run-enable operation is made by a driver and a non-running state is switched to a running state, shift position recognizing control is executed for recognizing an initial switching position appearing at the beginning when the running state is established, by driving the actuator in response to switching position information indicative of the switching position on a stage before the running state is established, wherein: the non-running state is configured to be switched to the running state prior to the execution of the run-enable operation; and updating of the switching position information, stored in the switching position information storage device, is permitted to be executed subjected to the switching position recognizing control being executed.Type: ApplicationFiled: June 21, 2012Publication date: December 6, 2012Inventors: Ichiro KITAORI, Takahiko TSUTSUMI, Osamu KANAI, Koki UENO, Keisuke SEKIYA, Toshinari SUZUKI
-
Publication number: 20120309590Abstract: A vehicular shift control apparatus for a vehicle provided with a parking lock device selectively switched to a locking position in which rotation of wheels of the vehicle is prevented and a non-locking position in which the rotation of the wheels is not prevented, by an operation of an electrically operated actuator, the vehicular shift control apparatus being configured to perform a failure diagnosis to determine whether the actuator is operable or not, the vehicular shift control apparatus includes: the vehicular shift control apparatus permits the operation of the actuator if a supply voltage to the actuator is raised from a value lower than a predetermined threshold supply voltage value to a value not lower than the threshold supply voltage value after a determination that the actuator is inoperable is obtained in the failure diagnosis.Type: ApplicationFiled: August 14, 2012Publication date: December 6, 2012Inventors: Osamu KANAI, Takahiko Tsutsumi, Ichiro Kitaori, Toshinari Suzuki, Hiroatsu Endo, Koki Ueno, Keisuke Sekiya
-
Patent number: 8310873Abstract: A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path of the memory cell, a word line electrically connected to the gate electrode, a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell, a row decoder electrically connected to the word line and configured to apply a read voltage at which the memory cell is set to an ON state to the word line, and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded.Type: GrantFiled: September 14, 2011Date of Patent: November 13, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Koki Ueno, Hiroyuki Nagashima
-
Publication number: 20120281487Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of memory cell units which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series, a voltage generator circuit which generates a voltage to be applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit. The control circuit, when writing data into the memory cell array, performs control so as to apply a first write pass voltage to unselected word lines in the memory cell units and, after a selected word line has reached a write voltage, further apply a voltage to the unselected word lines until a second write pass voltage higher than the first write pass voltage has been reached.Type: ApplicationFiled: November 3, 2011Publication date: November 8, 2012Inventors: Manabu SAKANIWA, Koki Ueno, Shigefumi Irieda, Eietsu Takahashi, Yasuhiro Shiino
-
Publication number: 20120281477Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array includes a plurality of cell units each composed of a plurality of memory cells which are arranged at intersections of a plurality of bit lines and a plurality of word lines and whose current paths are connected in series and select transistors each connected to either end of the series connection, a voltage generator circuit which generates a voltage applied to the memory cell array, and a control circuit which controls the memory cell array and the voltage generator circuit.Type: ApplicationFiled: December 1, 2011Publication date: November 8, 2012Inventors: Manabu Sakaniwa, Koki Ueno, Shigefumi Irieda, Eietsu Takahashi, Yasuhiro Shiino, Daisuke Kouno
-
Publication number: 20120269001Abstract: A non-volatile semiconductor memory device according to one embodiment of the present invention includes a memory cell array and a control unit. The control unit is configured to control a repeat of an erase operation, an erase verify operation, and a step-up operation. The control unit is configured to perform a soft-programming operation of setting the memory cells from an over-erased state to a first threshold voltage distribution state when, in a series of erase operations, the number of erase voltage applications is more than a first number and less than a second number (the first number<the second number). The control unit is configured not to perform the soft-programming operation when the number of erase voltage applications is equal to or less than the first number or equal to or more than the second number.Type: ApplicationFiled: October 25, 2011Publication date: October 25, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koki UENO, Eietsu Takahashi, Shigefumi Irieda, Yasuhiro Shiino, Manabu Sakaniwa
-
Publication number: 20120257453Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: September 27, 2011Publication date: October 11, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
-
Publication number: 20120252628Abstract: When a P lock state is set on the basis of a predetermined request signal for setting the P lock state, a P position indicator lamp (62) is turned on or off on the basis of the status of power supplied to the vehicle (10). For example, when the P lock state is set, the P position indicator lamp (62) is turned off when the power status is an ALL-OFF status where a combination meter (56), or the like, is not turned on or is raised to an ACC-ON status; whereas, when the P lock state is set, the P position indicator lamp (62) is turned on when the power status is an IG-ON status, when the power status is changed from the IG-ON status during vehicle driving to the ACC-ON status, or within a predetermined period of time from when the power status is changed from the IG-ON status to the ALL-OFF status.Type: ApplicationFiled: November 5, 2010Publication date: October 4, 2012Inventors: Takahiko Tsutsumi, Keisuke Sekiya, Koki Ueno, Ichiro Kitaori, Toshinari Suzuki
-
Publication number: 20120248524Abstract: In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.Type: ApplicationFiled: June 11, 2012Publication date: October 4, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Toshitake YAEGASHI, Koki UENO
-
Publication number: 20120206972Abstract: A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.Type: ApplicationFiled: September 7, 2011Publication date: August 16, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
-
Patent number: 8217468Abstract: In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.Type: GrantFiled: May 20, 2011Date of Patent: July 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshitake Yaegashi, Koki Ueno
-
Patent number: 8174899Abstract: When data is written to a memory cell transistor, a write controller controls in such a manner that a verification operation subsequent to a program operation is carried out while a program voltage is increased stepwise for each program operation. The write controller controls in such a manner that a verification operation subsequent to a program operation by which a threshold voltage of a memory cell transistor to be written has become equal to or higher than a verification level for the first time is carried out twice or more at the same verification level, verification operations of the second and subsequent times are carried out after a second program operation which is carried out with the memory cell transistor set in an unselected state.Type: GrantFiled: April 15, 2011Date of Patent: May 8, 2012Assignee: Kabushiki Kaisha ToshibaInventor: Koki Ueno
-
Publication number: 20120072083Abstract: When initial drive control for an actuator driving a shift switch mechanism is completed, a P-ECU determines whether an IG signal is received. In the case where the P-ECU has not received the IG signal at the time when the initial drive control is completed, the P-ECU temporarily keeps the actuator in a state where the initial drive control is completed. In the case where the P-ECU receives the IG signal in the period from completion of the initial drive control to the time when a predetermined time T2 has elapsed since completion of the initial drive control, the P-ECU executes P wall press control when the P-ECU receives the IG signal.Type: ApplicationFiled: June 3, 2009Publication date: March 22, 2012Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takahiko Tsutsumi, Ichiro Kitaori, Koki Ueno, Keisuke Sekiya, Toshinari Suzuki
-
Publication number: 20120022756Abstract: A shift control device is provided for a vehicle of shift-by-wire type having shift operation detecting means electrically detecting a shift operation of a driver, range switching means switching a shift range in response to the shift operation of the driver, failure detecting means detecting a failure in a shift operation detection executed by the shift operation detecting means, and vehicle state detecting means detecting a vehicle state upon detection of the failure in the shift operation detection, the range switching means being switched to a fail-safe mode, when the shift operation detection is recovered from a failed state to a normal state and the range switching means is switched from the fail-safe mode to a normal control mode, a recovery condition for determining switching of the fail-safe mode to the normal control mode being altered depending on the vehicle state.Type: ApplicationFiled: March 8, 2010Publication date: January 26, 2012Inventors: Koki Ueno, Takahiko Tsutsumi, Ichiro Kitaori, Hiroatsu Endo, Takashi Yuma, Masayuki Matsui
-
Publication number: 20120022754Abstract: It is provided a shifting control device for vehicle for electrically controlling a switching of a transmission to a parking range for performing a parking lock in response to an operation by a driver, the shifting control device for vehicle configured to determine the switching to the parking range when the driver performs a predetermined operation for switching to the parking range, based on whether plural vehicle speed signals different in response relative to an actual vehicle speed satisfy a predetermined condition; and the switching to the parking range being determined (i) using a corrected value obtained by correcting a vehicle speed signal having a slower response such that a difference in a vehicle speed based on the vehicle speed signal having the slower response and a vehicle speed signal having a quicker response is suppressed, or (ii) using a corrected value obtained by correcting a predetermined vehicle-speed threshold value associated with the vehicle speed signal having the quicker response sType: ApplicationFiled: March 3, 2010Publication date: January 26, 2012Inventor: Koki Ueno