Patents by Inventor Koki Ueno
Koki Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210005270Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: September 21, 2020Publication date: January 7, 2021Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Patent number: 10818362Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: October 9, 2019Date of Patent: October 27, 2020Assignee: Toshiba Memory CorporationInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Publication number: 20200324791Abstract: A vehicle control device is applied to a vehicle including at least a shift control system configured to switch a shift range. The vehicle control device is configured to control the vehicle to perform autonomous driving travel without depending on an operation of a driver in at least one driving operation. The vehicle control device includes a controller. The controller is configured to determine the propriety of travel by the autonomous driving travel according to a type of abnormality that occurs in the shift control system. The controller is configured to perform travel control of the vehicle according to the propriety of the travel by the autonomous driving travel.Type: ApplicationFiled: March 18, 2020Publication date: October 15, 2020Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Koki UENO, Yusuke Nakade, Kazuhiro Ozawa
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Patent number: 10803950Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: GrantFiled: May 23, 2019Date of Patent: October 13, 2020Assignee: Toshiba Memory CorporationInventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
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Publication number: 20200309254Abstract: A control device for a vehicle including (i) a power transmission device, (ii) a shift operation device that is to be operated by a driver of the vehicle to an operation position corresponding to a shift position of the power transmission device, and (iii) a switching device for switching the shift position of the power transmission device through actuation of an actuator. The control device is configured, upon occurrence of a momentary interruption of a control-device electric-power source that is supplied with an electric power from a vehicle electric-power source, to not perform an initial position learning process for setting a reference position of the actuator, until a shift switching operation for switching the shift position of the power transmission device is performed by a driver of the vehicle.Type: ApplicationFiled: March 30, 2020Publication date: October 1, 2020Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yusuke YAMAUCHI, Koki UENO, Yusuke NAKADE, Ichiro KITAORI
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Patent number: 10783975Abstract: A semiconductor memory device includes first and second memory transistors and first and second word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured such that a first write operation to the first memory transistor, a second write operation to the second memory transistor, a third write operation to the first memory transistor, and a fourth write operation to the second memory transistor are executed in this order. In the first and second write operations, data write is performed using only a program operation. In the third and fourth write operations, data write is performed using the program operation and the verify operation.Type: GrantFiled: September 5, 2019Date of Patent: September 22, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shimura, Koki Ueno, Go Shikata
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Publication number: 20200273530Abstract: A semiconductor memory device includes first and second memory transistors and first and second word lines connected to gate electrodes of the memory transistors. The semiconductor memory device is configured such that a first write operation to the first memory transistor, a second write operation to the second memory transistor, a third write operation to the first memory transistor, and a fourth write operation to the second memory transistor are executed in this order. In the first and second write operations, data write is performed using only a program operation. In the third and fourth write operations, data write is performed using the program operation and the verify operation.Type: ApplicationFiled: September 5, 2019Publication date: August 27, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shimura, Koki Ueno, Go Shikata
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Patent number: 10739767Abstract: An operation control apparatus that controls a changeover from an automatic operation mode in which a vehicle is automatically operated to a manual operation mode in which the vehicle is manually operated, the vehicle includes a parking lock mechanism, and a sensor, the operation control apparatus includes an electronic control unit configured to: i) control the vehicle such that the vehicle is automatically operated, based on information received from the sensor; ii) determine whether or not a first condition is established; and iii) activate the parking lock mechanism, and change over an operation mode of the vehicle from the automatic operation mode to the manual operation mode after establishing the parking lock state, when the first condition is not established. The first condition is that the automatic operation mode can be continued.Type: GrantFiled: January 23, 2018Date of Patent: August 11, 2020Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Koki Ueno
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Patent number: 10625604Abstract: A vehicle shift control device comprises: a shift position deciding portion deciding a shift position of a shift operating device based on a sensor signal output according to an operation of the shift operating device; and a drive power output command portion selecting a shift range based on a shift position determination signal output from the shift position deciding portion to cause a vehicle to run, when a communication abnormality has occurred so that the shift position determination signal is not transmitted from the shift position deciding portion to the drive power output command portion, the vehicle shift control device selecting a shift range maintained at the time of occurrence of the communication abnormality of the shift position determination signal if a vehicle speed is equal to or greater than a predetermined value, and selecting a neutral range if the vehicle speed is less than the predetermined value.Type: GrantFiled: January 12, 2018Date of Patent: April 21, 2020Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi Yuma, Koki Ueno, Masato Tateno, Yusuke Nakade
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Publication number: 20200043558Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: October 9, 2019Publication date: February 6, 2020Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIINO, Eietsu Takahashi, Koki Ueno
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Patent number: 10490286Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: December 4, 2018Date of Patent: November 26, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Publication number: 20190305154Abstract: The present disclosure is to provide a multi-junction light energy conversion element including a material having a band gap suitable for a light energy conversion layer located upstream in an incidence direction of light. The present disclosure provides a light energy conversion element, comprising a first light energy conversion layer containing SrZn2N2 and a second light energy conversion layer containing an light energy conversion material. The light energy conversion material has a narrower band gap than the SrZn2N2.Type: ApplicationFiled: December 18, 2018Publication date: October 3, 2019Inventors: KOKI UENO, RYOSUKE KIKUCHI, TORU NAKAMURA, TAKAHIRO KURABUCHI, YASUSHI KANEKO, KAZUHITO HATO, FUMIYASU OBA, YU KUMAGAI
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Publication number: 20190279716Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: ApplicationFiled: May 23, 2019Publication date: September 12, 2019Applicant: Toshiba Memory CorporationInventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
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Patent number: 10410725Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.Type: GrantFiled: September 18, 2018Date of Patent: September 10, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Koki Ueno, Yasuhiro Shiino, Asuka Kaneda
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Patent number: 10378646Abstract: A shift range is selected based on a vehicle speed or acceleration of a vehicle and a shift range kept by a drive unit at the time when it is determined that there is a malfunction in shift sensors. Thus, it is possible to avoid a disabled self-propelled state resulting from a change into a neutral range through a fail-safe operation and keep limp home running.Type: GrantFiled: October 26, 2017Date of Patent: August 13, 2019Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi Yuma, Koki Ueno, Masato Tateno, Yusuke Nakade
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Publication number: 20190220006Abstract: A control apparatus for a vehicle makes the vehicle travel without depending on operation of a shift operation apparatus by a driver, even in a case where a detection abnormality by which a shift operation position of the shift operation apparatus becomes indefinite has occurred.Type: ApplicationFiled: December 31, 2018Publication date: July 18, 2019Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Koki UENO
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Patent number: 10347338Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: GrantFiled: September 8, 2017Date of Patent: July 9, 2019Assignee: Toshiba Memory CorporationInventors: Yasuhiro Shimura, Tomoki Higashi, Sumito Ohtsuki, Junichi Kijima, Keisuke Yonehama, Shinichi Oosera, Yuki Kanamori, Hidehiro Shiga, Koki Ueno
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Publication number: 20190108885Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: December 4, 2018Publication date: April 11, 2019Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Patent number: 10186321Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: March 8, 2018Date of Patent: January 22, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Publication number: 20190019559Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.Type: ApplicationFiled: September 18, 2018Publication date: January 17, 2019Inventors: Koki UENO, Yasuhiro SHIINO, Asuka KANEDA