Patents by Inventor Koki Ueno
Koki Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10180184Abstract: A detecting device includes a shift selector, a magnet disposed in the shift selector, four or more sensors arranged at positions facing the magnet and an ECU. The ECU is configured to (i) determine a shift position based on signals output from the four or more sensors when the magnet is relatively displaced with respect to the four or more sensors in response to an operation of the shift selector, (ii) determine the shift position based on signals output from three or more of the four or more sensors determined to be normal when any one of the four or more sensors is abnormal, and (iii) determine the abnormality based on whether or not the three or more sensors output, during the traveling of the vehicle, a signal to a shift position pertaining to a case of traveling in the direction opposite to a traveling direction of the vehicle.Type: GrantFiled: August 3, 2015Date of Patent: January 15, 2019Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takahiko Tsutsumi, Masato Tateno, Koki Ueno, Hiroshi Shibata
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Patent number: 10166953Abstract: When a P lock state is set on the basis of a predetermined request signal for setting the P lock state, a P position indicator lamp (62) is turned on or off on the basis of the status of power supplied to the vehicle (10). For example, when the P lock state is set, the P position indicator lamp (62) is turned off when the power status is an ALL-OFF status where a combination meter (56), or the like, is not turned on or is raised to an ACC-ON status; whereas, when the P lock state is set, the P position indicator lamp (62) is turned on when the power status is an IG-ON status, when the power status is changed from the IG-ON status during vehicle driving to the ACC-ON status, or within a predetermined period of time from when the power status is changed from the IG-ON status to the ALL-OFF status.Type: GrantFiled: November 5, 2010Date of Patent: January 1, 2019Assignee: Toyota Jidosha Kabushiki KaishaInventors: Takahiko Tsutsumi, Keisuke Sekiya, Koki Ueno, Ichiro Kitaori, Toshinari Suzuki
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Patent number: 10109353Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.Type: GrantFiled: June 30, 2017Date of Patent: October 23, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Koki Ueno, Yasuhiro Shiino, Asuka Kaneda
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Publication number: 20180268906Abstract: According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.Type: ApplicationFiled: September 8, 2017Publication date: September 20, 2018Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIMURA, Tomoki HIGASHI, Sumito OHTSUKI, Junichi KIJIMA, Keisuke YONEHAMA, Shinichi OOSERA, Yuki KANAMORI, Hidehiro SHIGA, Koki UENO
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Publication number: 20180217592Abstract: An operation control apparatus that controls a changeover from an automatic operation mode in which a vehicle is automatically operated to a manual operation mode in which the vehicle is manually operated, the vehicle includes a parking lock mechanism, and a sensor, the operation control apparatus includes an electronic control unit configured to: i) control the vehicle such that the vehicle is automatically operated, based on information received from the sensor; ii) determine whether or not a first condition is established; and iii) activate the parking lock mechanism, and change over an operation mode of the vehicle from the automatic operation mode to the manual operation mode after establishing the parking lock state, when the first condition is not established. The first condition is that the automatic operation mode can be continued.Type: ApplicationFiled: January 23, 2018Publication date: August 2, 2018Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Koki UENO
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Publication number: 20180201126Abstract: A vehicle shift control device comprises: a shift position deciding portion deciding a shift position of a shift operating device based on a sensor signal output according to an operation of the shift operating device; and a drive power output command portion selecting a shift range based on a shift position determination signal output from the shift position deciding portion to cause a vehicle to run, when a communication abnormality has occurred so that the shift position determination signal is not transmitted from the shift position deciding portion to the drive power output command portion, the vehicle shift control device selecting a shift range maintained at the time of occurrence of the communication abnormality of the shift position determination signal if a vehicle speed is equal to or greater than a predetermined value, and selecting a neutral range if the vehicle speed is less than the predetermined value.Type: ApplicationFiled: January 12, 2018Publication date: July 19, 2018Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi YUMA, Koki UENO, Masato TATENO, Yusuke NAKADE
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Publication number: 20180197616Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: March 8, 2018Publication date: July 12, 2018Applicant: Toshiba Memory CorporationInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Publication number: 20180172144Abstract: A shift range is selected based on a vehicle speed or acceleration of a vehicle and a shift range kept by a drive unit at the time when it is determined that there is a malfunction in shift sensors. Thus, it is possible to avoid a disabled self-propelled state resulting from a change into a neutral range through a fail-safe operation and keep limp home running.Type: ApplicationFiled: October 26, 2017Publication date: June 21, 2018Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi YUMA, Koki UENO, Masato TATENO, Yusuke NAKADE
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Patent number: 9947415Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: May 18, 2017Date of Patent: April 17, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Publication number: 20180005698Abstract: A memory device includes a plurality of memory cell transistors, a word line electrically connected to gates of the memory cell transistors, and a control circuit configured to perform programming of the memory cell transistors to a plurality of different threshold voltage ranges in a plurality of loops, each loop including a program operation and a program verification. The different threshold voltage ranges include a first threshold voltage range and a second threshold voltage range that is at a higher voltage than the first threshold voltage range. Further, during the program operation, the control circuit applies a program voltage to the word line, the program voltage increasing for each subsequent loop, an amount of increase of the program voltage when programming to the second threshold voltage range being set in accordance with a number of loops required to complete programming to the first threshold voltage range.Type: ApplicationFiled: June 30, 2017Publication date: January 4, 2018Inventors: Koki UENO, Yasuhiro SHIINO, Asuka KANEDA
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Publication number: 20170256321Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Publication number: 20170219089Abstract: A detecting device includes a shift selector, a magnet disposed in the shift selector, four or more sensors arranged at positions facing the magnet and an ECU. The ECU is configured to (i) determine a shift position based on signals output from the four or more sensors when the magnet is relatively displaced with respect to the four or more sensors in response to an operation of the shift selector, (ii) determine the shift position based on signals output from three or more of the four or more sensors determined to be normal when any one of the four or more sensors is abnormal, and (iii) determine the abnormality based on whether or not the three or more sensors output, during the traveling of the vehicle, a signal to a shift position pertaining to a case of traveling in the direction opposite to a traveling direction of the vehicle.Type: ApplicationFiled: August 3, 2015Publication date: August 3, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takahiko TSUTSUMI, Masato TATENO, Koki UENO, Hiroshi SHIBATA
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Patent number: 9691489Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: September 13, 2016Date of Patent: June 27, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Patent number: 9611932Abstract: When initial drive control for an actuator driving a shift switch mechanism is completed, a P-ECU determines whether an IG signal is received. In the case where the P-ECU has not received the IG signal at the time when the initial drive control is completed, the P-ECU temporarily keeps the actuator in a state where the initial drive control is completed. In the case where the P-ECU receives the IG signal in the period from completion of the initial drive control to the time when a predetermined time T2 has elapsed since completion of the initial drive control, the P-ECU executes P wall press control when the P-ECU receives the IG signal.Type: GrantFiled: June 3, 2009Date of Patent: April 4, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takahiko Tsutsumi, Ichiro Kitaori, Koki Ueno, Keisuke Sekiya, Toshinari Suzuki
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Publication number: 20170069393Abstract: A memory device according to one embodiment includes cell transistors; and a controller which is configured to write data in a first page and a second page and read data from the first and second pages, and when the controller writes data in the second page of the cell transistors with data written in the first page, reads data from the first page, uses a first value or a second value for a first parameter based on the read data, and uses a third value or a fourth value for a second parameter based on the read data.Type: ApplicationFiled: November 10, 2015Publication date: March 9, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Koki UENO, Yasuhiro SHllNO, Asuka KANEDA, Aki KO
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Patent number: 9580051Abstract: An ECU executes a program including: a step of starting up an SBW system if lock release is detected; a step of starting up a timer if setting of a reference location corresponding to a P position has been completed; and a step of stopping the SBW system if a power supply is not turned on until a predetermined time T has elapsed.Type: GrantFiled: June 18, 2009Date of Patent: February 28, 2017Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventor: Koki Ueno
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Publication number: 20160379717Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: ApplicationFiled: September 13, 2016Publication date: December 29, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro SHIINO, Eietsu TAKAHASHI, Koki UENO
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Patent number: 9481361Abstract: A control apparatus for a vehicle provided with an engine, an electric motor, and a damper disposed in a power transmitting path between said engine and said electric motor, wherein said engine is started with its speed being raised by a drive force of said electric motor, wherein said damper has characteristics of generating a larger hysteresis torque during its torsion in a negative direction of transmission of the drive force from said electric motor toward said engine, than a hysteresis torque generated during its torsion in a positive direction of transmission of a drive force from said engine toward said electric motor, said control apparatus comprising a hybrid control portion configured to ignite said engine by igniting said engine in the process of a rise of the speed of said engine while said damper is subjected to the torsion in the negative direction by said electric motor.Type: GrantFiled: January 21, 2013Date of Patent: November 1, 2016Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kenji Gotoda, Koji Hayashi, Koki Ueno
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Patent number: 9472295Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.Type: GrantFiled: April 2, 2015Date of Patent: October 18, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yasuhiro Shiino, Eietsu Takahashi, Koki Ueno
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Publication number: 20160267989Abstract: A nonvolatile semiconductor memory device, includes a memory cell array, and a control circuit configured to control voltage applied to the memory cell array. The memory cell array includes: a plurality of first wiring lines extending in a first direction, a plurality of second wiring lines extending in a second direction intersecting with the first direction, and memory cells arranged in respective intersecting portions between the plurality of first wiring lines and the plurality of second wiring lines. The control circuit changes voltages applied to the plurality of first wiring lines and/or times during which voltages are applied to the plurality of first wiring lines independently in each of predetermined spatial periods.Type: ApplicationFiled: September 10, 2015Publication date: September 15, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuya OGURA, Yukihiro UTSUNO, Kazuhide SUZUKI, Koki UENO, Yasuhiro TOMITA, Makoto NAKASHIMA, Kazuhiko MURAKI, Satoshi AOKI