Abstract: Apertures in a circuit board or chip carrier are filled with a cured photosensitive dielectric material by substantially filling the apertures in the circuit board or chip carrier and applying a layer of a thickness to the circuit board or chip carrier with a positive photosensitive dielectric material, exposing the photosensitive dielectric material to actinic radiation in such a way as to leave material located in apertures unexposed to the radiation; baking the structure so as to harden the unexposed photosensitive dielectric material and developing the exposed dielectric material in order to remove it leaving behind cured photosensitive dielectric material in the apertures.

Abstract: A halogen-free dielectric resin mixture is described for use in microvia and other similar applications. The resin mixture contains a cyanate ester monomer or prepolymer a bismaleimide, an epoxy and a flame inhibiting compound selected from the group consisting of a phosphinic acid anhydride, a phosphonic acid andydride and a phosphonic acid half-ester. The flame inhibitor is present in an amount wherein the elemental phosphorus content is between about 2% and about 20% by weight, based on the weight of the resin mixture. The resin mixture can also include one or more coloring, fluorescent and UV absorbing agents. Prepregs based on the resin mixture with inorganic or organic reinforcing agents, as well as circuit boards and chip carriers made from the prepregs are also described. A resin coated article for use in microvia laser applications is likewise included.

Abstract: A semiconductor device having a thermoset-containing, dielectric material and methods for fabricating the same is provided. The device may take the form of a printed circuit board, an integrated circuit chip carrier, or the like. The dielectric material is a non-fibrillated, fluoropolymer matrix that has inorganic particles distributed therein and is impregnated with a thermoset material.

Abstract: A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.

Abstract: In accordance with the present invention, a method of treating the surface of an organic substrate, particularly a circuitized surface of an organic substrate, which method reduces the spread of adhesive resin that is subsequently deposited on the surface, is provided. This method comprises the steps of applying a treatment solution comprising a fatty acid compound, an alkalizing agent, and a solvent comprising water and from about 5% to about 90% by volume of an organic solvent selected from the group consisting of an alcohol, a glycol ether, and combinations thereof to the surface; and then removing substantially all of the solvent from the solution to provide a thin film on the surface of said substrate. The film comprises the fatty acids that were present in the treatment solution. In a preferred embodiment the treatment solution further comprises a chelating agent.

Abstract: The present invention relates to a method and structure for providing an interconnect between layers of a multilayer circuit board.

Abstract: The present invention relates to a structure for providing an interconnect between layers of a multilayer circuit board. The structure comprises a stack that includes at least one layer and a via opening that extends through at least one layer of the stack. Each individual via opening is filled with a solid conductive plug and each solid conductive plug has a first contact pad and a second contact pad.

Abstract: A halogen-free dielectric resin mixture is described for use in microvia and other similar applications. The resin mixture contains a cyanate ester monomer or prepolymer a bismaleimide, an epoxy and a flame inhibiting compound selected from the group consisting of a phosphinic acid anhydride, a phosphonic acid andydride and a phosphonic acid half-ester. The flame inhibitor is present in an amount wherein the elemental phosphorus content is between about 2% and about 20% by weight, based on the weight of the resin mixture. The resin mixture can also include one or more coloring, fluorescent and UV absorbing agents. Prepregs based on the resin mixture with inorganic or organic reinforcing agents, as well as circuit boards and chip carriers made from the prepregs are also described. A resin coated article for use in microvia laser applications is likewise included.

Abstract: Wire bond packages which mount encapsulated semiconductor chips, such as plastic ball grid array (PBGA) packages providing for the mounting of so-called flip-chips. The chips are overlaid with heat spreading perforated cap wherein the perforations are filled with an adhesive to prevent delamination caused by mismatches in the coefficients of thermal expansion, resulting in contractions which cause the entire package arrangement to warp, leading to delamination between an encapsulant and cap and resulting in failure of connect joints and the ball grid arrays.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: A method of forming a capacitive core structure and of forming a circuitized printed wiring board from the core structure and the resulting structures are provided. The capacitive core structure is formed by providing a central conducting plane of a sheet of conductive material and forming at least one clearance hole in the central conducting plane. First and second external conducting planes are laminated to opposite sides of the ground plane with a film of dielectric material between each of the first and second external planes and the central conducting plane. At least one clearance hole is formed in each of the first and second external planes. A circuitized wiring board structure can be formed by laminating a capacitive core structure between two circuitized structures. The invention also relates to the structures formed by these methods.

Abstract: A composition usable in hole filling of a metal layer and to planarize the metal layer is provided. The metal layer is part of a substrate which can be part of a multilayer printed circuit board or chip carrier. The composition comprises a fluoropolymer dielectric metal, a filler material, and a coupling agent, the filler material having at least a partial coating of the coupling agent thereon.

Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

Abstract: The present invention relates to a method and structure for providing an interconnect between layers of a multilayer circuit board.

Abstract: The present invention provides a method of filling an at least one aperture in a semiconductor substrate by placing a sacrificial carrier structure on a surface of the substrate, wherein the structure comprises, a first layer, a fill material over the first layer, and a mask over the fill material having at least one opening therein, such that the opening at least partially aligns with the aperture in the substrate. Thereafter, the fill material is forced into the aperture by the application of heat and pressure, and the sacrificial carrier structure is removed.

Abstract: A laminate circuit structure assembly is provided that comprises at least two modularized circuitized plane subassemblies; a joining layer located between each of the subassemblies and wherein the subassemblies and joining layer are bonded together with a cured dielectric from a bondable, curable dielectric. The subassemblies and joining layer are electrically interconnected with bondable electrically conductive material. The joining layer comprises dielectric layers disposed about an internal electrically conductive layer. The electrically conductive layer has a via and the dielectric layers each have a via of smaller diameter than the vias in the electrically conductive layer and are aligned with the vias in the electrically conductive layer. The vias are filled with electrically bondable electrically conductive material for providing electrical contact between the subassemblies.

Abstract: A method and structure relating to multisegmented plated through holes. A substrate includes a dielectric layer sandwiched between a first laminate layer and a second laminate layer. A through hole is formed through the substrate. The through hole passes through nonplatable dielectric material within the dielectric layer. As a result, subsequent seeding and electroplating of the through hole results in a conductive metal plating forming at a wall of the through hole on a segment of the first laminate layer and on a segment of the second laminate layer, but not on the nonplatable dielectric material of the dielectric layer. Thus, the conductive metal plating is not continuous from the first laminate layer to the second laminate layer.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: A method of forming a core for and forming a composite wiring board. The core has an electrically conductive coating on at least one face of a dielectric substrate. At least one opening is formed through the substrate extending from one face to the other and through each conductive coating. An electrically conductive material is dispensed in each of the openings extending through the conducting coating. At least a portion of the surface of the conductive coating on one face is removed to allow a nub of the conductive material to extend above the substrate face and any remaining conductive material to thereby form a core that can be electrically joined face-to-face with a second core member or other circuitized structure.

Abstract: A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.