Patents by Inventor Kuen-Ting Shiu

Kuen-Ting Shiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170075062
    Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.
    Type: Application
    Filed: November 29, 2016
    Publication date: March 16, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9595805
    Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20170069491
    Abstract: A method comprises providing a sacrificial release layer on a base substrate; forming a device layer on the sacrificial release layer; depositing a metal stressor layer on the device layer; etching the sacrificial release layer; and using epitaxial lift off to release the device layer and the metal stressor layer from the base substrate.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9590393
    Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9589791
    Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Szu-Lin Cheng, Isaac Lauer, Kuen-Ting Shiu, Jeng-Bang Yau
  • Publication number: 20170062232
    Abstract: A method for performing epitaxial lift-off allowing reuse of a III-V substrate to grow III-V devices is presented. A sample is received comprising a growth substrate with a top surface, a sacrificial layer on the top surface, and a device layer on the sacrificial layer. This substrate is supported inside a container and the container is filled with a wet etchant such that the wet etchant progressively etches away the sacrificial layer and the device layer lifts away from the growth substrate. While filling the container with the wet etchant, the sample is supported in the container such that the top surface of the growth substrate is non-parallel with an uppermost surface of the wet etchant. Performed in this manner, the lift-off process requires little individual setup of the sample, and is capable of batch processing and high throughput.
    Type: Application
    Filed: August 28, 2015
    Publication date: March 2, 2017
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Leathen Shi, Kuen-Ting Shiu
  • Patent number: 9570296
    Abstract: A method of forming a semiconducting material includes depositing a graded buffer on a substrate to form a graded layer of an indium (In) containing III-V material, the In containing III-V material being indium-gallium-arsenic (InGaAs) or indium-aluminum-arsenic (InAlAs) and comprising In in an increasing atomic gradient up to 35 atomic % (at. %) based on total atomic weight of InGa or InAl; and forming a layer of InGaAs on the graded layer, the layer of InGaAs comprising about 25 to about 100 at. % In based on total atomic weight of InGa.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9564494
    Abstract: A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown material is formed on the substrate and includes a first region in or near the cavity and a second region outside the first region wherein the second region contains fewer defects than the first region.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: February 7, 2017
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, David L. Rath, Devendra K. Sadana, Kuen-Ting Shiu, Brent A. Wacaser
  • Publication number: 20170033305
    Abstract: A photovoltaic device that includes an organic or quantum dot sensitizer layer for absorbing light spectra and providing excitons. The sensitizer layer may include metal particles embedded therein for increased exciton transfer efficiency. The photovoltaic device may further include a junction comprising an electron donor layer and electron acceptor layer for charge carrier transport.
    Type: Application
    Filed: July 31, 2015
    Publication date: February 2, 2017
    Inventors: Cheng-Wei Cheng, Jeehwan Kim, Ning Li, Kuen-Ting Shiu
  • Patent number: 9548355
    Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 17, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Szu-Lin Cheng, Isaac Lauer, Kuen-Ting Shiu, Jeng-Bang Yau
  • Publication number: 20160379820
    Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.
    Type: Application
    Filed: November 23, 2015
    Publication date: December 29, 2016
    Inventors: Szu-Lin Cheng, Isaac Lauer, Kuen-Ting Shiu, Jeng-Bang Yau
  • Publication number: 20160380049
    Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.
    Type: Application
    Filed: June 24, 2015
    Publication date: December 29, 2016
    Inventors: Szu-Lin Cheng, Isaac Lauer, Kuen-Ting Shiu, Jeng-Bang Yau
  • Patent number: 9508640
    Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: November 29, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Cheng-Wei Cheng, Szu-Lin Cheng, Keith E. Fogel, Edward W. Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9496347
    Abstract: A method of forming a semiconductor device includes: providing a patterned structure comprising a silicon substrate and dielectric stacks deposited on the silicon substrate, the dielectric stacks forming trenches exposing a plurality of surface portions of the substrate within the trenches; forming one or more epitaxial buffer layers within the trenches on the exposed surface portions of the substrate; and growing a semiconductor material on the epitaxial buffer layer that is the furthest away from the substrate; wherein each of the one or more epitaxial buffer layers and the semiconductor material has less than about 3% lattice mismatch to the layer immediately beneath the one or more epitaxial buffer layer and the semiconductor material.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Amlan Majumdar, Kuen-Ting Shiu, Jeng-Bang Yau
  • Publication number: 20160322226
    Abstract: The present invention provides ART techniques with reduced LER. In one aspect, a method of ART with reduced LER is provided which includes the steps of: providing a silicon layer separated from a substrate by a dielectric layer; patterning one or more ART lines in the silicon layer selective to the dielectric layer; contacting the silicon layer with an inert gas at a temperature, pressure and for a duration sufficient to cause re-distribution of silicon along sidewalls of the ART lines patterned in the silicon layer; using the resulting smoothened, patterned silicon layer to pattern ART trenches in the dielectric layer; and epitaxially growing a semiconductor material up from the substrate at the bottom of each of the ART trenches, to form fins in the ART trenches.
    Type: Application
    Filed: July 11, 2016
    Publication date: November 3, 2016
    Inventors: Guy Cohen, Katherine L. Saenger, Kuen-Ting Shiu
  • Publication number: 20160301192
    Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.
    Type: Application
    Filed: June 21, 2016
    Publication date: October 13, 2016
    Inventors: Cheng-Wei Cheng, Frank R. Libsch, Tak H. Ning, Uzma Rana, Kuen-Ting Shiu
  • Patent number: 9459797
    Abstract: A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: October 4, 2016
    Assignee: GLOBALFOUNDRIES, INC
    Inventors: Christos Dimitrakopoulos, Augustin J. Hong, Jeehwan Kim, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20160284930
    Abstract: A method of forming, and corresponding structure, of an LED device where an LED and the contacts for the device are formed on a surface of the substrate, and the substrate is spalled just below the surface of the substrate.
    Type: Application
    Filed: March 23, 2015
    Publication date: September 29, 2016
    Inventors: Can Bayram, Stephen W. Bedell, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20160252677
    Abstract: An electrical device that in one embodiment includes a first semiconductor device positioned on a first portion of a type IV semiconductor substrate, and an optoelectronic light emission device of type III-V semiconductor materials that is in electrical communication with the first semiconductor device. The optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type IV semiconductor substrate. A dielectric waveguide is present on a second portion of the type IV semiconductor substrate. An optoelectronic light detection device of type III-V semiconductor material is present on a third portion of the type IV semiconductor device. The dielectric waveguide is positioned between and aligned with the optoelectronic light detection device and optoelectronic light emission device to transmit a light signal from the optoelectronic light emission device to the optoelectronic light detection device.
    Type: Application
    Filed: May 12, 2016
    Publication date: September 1, 2016
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9431301
    Abstract: A semiconductor structure includes a plurality of semiconductor fins located on a semiconductor substrate, in which each of the semiconductor fins comprises a sequential stack of a buffered layer including a III-V semiconductor material and a channel layer including a III-V semiconductor material. The semiconductor structure further includes a gap filler material surrounding the semiconductor fins and including a plurality of trenches therein. The released portions of the channel layers of the semiconductor fins located in the trenches constitute nanowire channels of the semiconductor structure, and opposing end portions of the channel layers of the semiconductor fins located outside of the trenches constitute a source region and a drain region of the semiconductor structure, respectively. In addition, the semiconductor structure further includes a plurality of gates structures located within the trenches that surround the nanowire channels in a gate all around configuration.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: August 30, 2016
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Szu Lin Cheng, Isaac Lauer, Kuen-Ting Shiu, Jeng-Bang Yau