Patents by Inventor Kuen-Ting Shiu

Kuen-Ting Shiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160233361
    Abstract: A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
    Type: Application
    Filed: April 7, 2016
    Publication date: August 11, 2016
    Inventors: KEITH E. FOGEL, JEEHWAN KIM, JAE-WOONG NAH, DEVENDRA K. SADANA, KUEN-TING SHIU
  • Patent number: 9412744
    Abstract: After forming a first trench and a second trench extending through a top elemental semiconductor layer present on a substrate including, from bottom to top, a handle substrate, a compound semiconductor template layer and a buried insulator layer to define a top elemental semiconductor layer portion for a p-type metal-oxide-semiconductor transistor, the second trench is vertically expanded through the buried insulator layer to provide an expanded second trench that exposes a top surface of the compound semiconductor template layer at a bottom of the expanded second trench. A stack of a compound semiconductor buffer layer and a top compound semiconductor layer is epitaxially grown on the compound semiconductor template layer within the expanded second trench for an n-type metal-oxide-semiconductor transistor.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20160226222
    Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.
    Type: Application
    Filed: April 11, 2016
    Publication date: August 4, 2016
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20160225768
    Abstract: After forming a first trench and a second trench extending through a top elemental semiconductor layer present on a substrate including, from bottom to top, a handle substrate, a compound semiconductor template layer and a buried insulator layer to define a top elemental semiconductor layer portion for a p-type metal-oxide-semiconductor transistor, the second trench is vertically expanded through the buried insulator layer to provide an expanded second trench that exposes a top surface of the compound semiconductor template layer at a bottom of the expanded second trench. A stack of a compound semiconductor buffer layer and a top compound semiconductor layer is epitaxially grown on the compound semiconductor template layer within the expanded second trench for an n-type metal-oxide-semiconductor transistor.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Inventors: Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9406530
    Abstract: The present invention provides ART techniques with reduced LER. In one aspect, a method of ART with reduced LER is provided which includes the steps of: providing a silicon layer separated from a substrate by a dielectric layer; patterning one or more ART lines in the silicon layer selective to the dielectric layer; contacting the silicon layer with an inert gas at a temperature, pressure and for a duration sufficient to cause re-distribution of silicon along sidewalls of the ART lines patterned in the silicon layer; using the resulting smoothened, patterned silicon layer to pattern ART trenches in the dielectric layer; and epitaxially growing a semiconductor material up from the substrate at the bottom of each of the ART trenches, to form fins in the ART trenches.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: August 2, 2016
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Katherine L. Saenger, Kuen-Ting Shiu
  • Patent number: 9407066
    Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: August 2, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Cheng-Wei Cheng, Frank R. Libsch, Tak H. Ning, Uzma Rana, Kuen-Ting Shiu
  • Patent number: 9406566
    Abstract: A method of forming a semiconductor device is provided. The method includes depositing an aluminum-base interlayer on a silicon substrate, the aluminum-base interlayer having a thickness of less than about 100 nanometers; and growing a III-V compound material on the aluminum-base interlayer. The aluminum-base interlayer deposited directly on silicon allows for continuous and planar growth of III-V compound materials on the interlayer, which facilitates the manufacture of high quality electronic devices.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: August 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Sanghoon Lee, Kuen-Ting Shiu
  • Patent number: 9401583
    Abstract: A method of forming a laser on silicon using aspect ratio trapping (ART) growth. The method may include; forming a first insulator layer on a substrate; etching a trench in the first insulator layer exposing a top surface of the substrate; forming a buffer layer in the trench using ART growth; forming a laser on the buffer layer, the laser includes at least an active region and a top cladding layer; and forming a top contact on the top cladding layer and a bottom contact on the substrate.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: July 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Effendi Leobandung, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9397226
    Abstract: An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 19, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Cheng-Wei Cheng, Wilfried E. Haensch, Amlan Majumdar, Kuen-Ting Shiu
  • Patent number: 9395489
    Abstract: An electrical device that in one embodiment includes a first semiconductor device positioned on a first portion of a type IV semiconductor substrate, and an optoelectronic light emission device of type III-V semiconductor materials that is in electrical communication with the first semiconductor device. The optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type IV semiconductor substrate. A dielectric waveguide is present on a second portion of the type IV semiconductor substrate. An optoelectronic light detection device of type III-V semiconductor material is present on a third portion of the type IV semiconductor device. The dielectric waveguide is positioned between and aligned with the optoelectronic tight detection device and optoelectronic light emission device to transmit a light signal from the optoelectronic light emission device to the optoelectronic light detection device.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: July 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9391144
    Abstract: A semiconductor structure including a (100) silicon substrate having a plurality openings located within the silicon substrate, wherein each opening exposes a surface of the silicon substrate having a (111) crystal plane. This structure further includes an epitaxial semiconductor material located on an uppermost surface of the (100) silicon substrate, and a gallium nitride material located adjacent to the surface of the silicon substrate having the (111) crystal plane and adjacent a portion of the epitaxial semiconductor material. The structure also includes at least one semiconductor device located upon and within the gallium nitride material and at least one other semiconductor device located upon and within the epitaxial semiconductor material.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: July 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Can Bayram, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20160172465
    Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.
    Type: Application
    Filed: February 19, 2016
    Publication date: June 16, 2016
    Inventors: Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9368407
    Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: June 14, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Stephen W. Bedell, Cheng-Wei Cheng, Devendra K. Sadana, Katherine L. Saenger, Kuen-Ting Shiu
  • Publication number: 20160149054
    Abstract: An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.
    Type: Application
    Filed: November 12, 2015
    Publication date: May 26, 2016
    Inventors: Anirban Basu, Cheng-Wei Cheng, Wilfried E. Haensch, Amlan Majumdar, Kuen-Ting Shiu
  • Patent number: 9344200
    Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: May 17, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9337281
    Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: May 10, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Cheng-Wei Cheng, Jack O. Chu, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9324853
    Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: April 26, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9318641
    Abstract: A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: April 19, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20160103278
    Abstract: An electrical device that in one embodiment includes a first semiconductor device positioned on a first portion of a type IV semiconductor substrate, and an optoelectronic light emission device of type III-V semiconductor materials that is in electrical communication with the first semiconductor device. The optoelectronic light emission device is positioned adjacent to the first semiconductor device on the first portion of the type IV semiconductor substrate. A dielectric waveguide is present on a second portion of the type IV semiconductor substrate. An optoelectronic light detection device of type III-V semiconductor material is present on a third portion of the type IV semiconductor device. The dielectric waveguide is positioned between and aligned with the optoelectronic tight detection device and optoelectronic light emission device to transmit a light signal from the optoelectronic light emission device to the optoelectronic light detection device.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 14, 2016
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20160105247
    Abstract: An electrical device that includes a first semiconductor device positioned on a first portion of a substrate and a second semiconductor device positioned on a third portion of the substrate, wherein the first and third portions of the substrate are separated by a second portion of the substrate. An interlevel dielectric layer is present on the first, second and third portions of the substrate. The interlevel dielectric layer is present over the first and second semiconductor devices. An optical interconnect is positioned over the second portion of the semiconductor substrate. At least one material layer of the optical interconnect includes an epitaxial material that is in direct contact with a seed surface within the second portion of the substrate through a via extending through the least one interlevel dielectric layer.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 14, 2016
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu