Patents by Inventor Kuen-Ting Shiu

Kuen-Ting Shiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160087160
    Abstract: A semiconductor device including a substrate structure including a semiconductor material layer that is present directly on a buried dielectric layer in a first portion of the substrate structure and an isolation dielectric material that is present directly on the buried dielectric layer in a second portion of the substrate structure. The semiconductor device further includes a III-V optoelectronic device that is present in direct contact with the isolation dielectric material in a first region of the second portion of the substrate structure. A dielectric wave guide is present in direct contact with the isolation dielectric material in a second region of the second portion of the substrate structure.
    Type: Application
    Filed: September 22, 2014
    Publication date: March 24, 2016
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9287115
    Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: March 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9287362
    Abstract: An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a fifth semiconductor layer, and a first dielectric layer. The etched first dielectric layer and a first drain contact are surrounded by a first spacer. The first drain contact is composed of the fifth semiconductor layer. A second drain contact composed of the fourth semiconductor layer, a channel composed of the third semiconductor layer, and a second source contact composed of the second semiconductor layer are formed. Additionally, first source contact composed of the first semiconductor is formed and a gate electrode is formed on a portion of the first source contact layer surrounding a portion of the first pillar and the second pillar.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: March 15, 2016
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Cheng-Wei Cheng, Wilfried E. Haensch, Amlan Majumdar, Kuen-Ting Shiu
  • Publication number: 20160072002
    Abstract: A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 10, 2016
    Inventors: KEITH E. FOGEL, JEEHWAN KIM, JAE-WOONG NAH, DEVENDRA K. SADANA, KUEN-TING SHIU
  • Patent number: 9263626
    Abstract: A material stack including an ohmic contact layer and a single crystalline semiconductor base substrate of a first conductivity type and having a surface Fermi level pinned close to a band edge (either the conduction band or valence band) is first provided. A stressor layer is then formed above the ohmic contact layer and a material portion of the single crystalline semiconductor base substrate is removed by a process referred to as spalling. A transparent conductive oxide layer is then formed on an exposed surface of the material portion of the single crystalline semiconductor base substrate that was removed by spalling.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Cheng-Wei Cheng, Ning Li, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9236251
    Abstract: Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: January 12, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Can Bayram, Cheng-Wei Cheng, Tak H. Ning, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 9231133
    Abstract: A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: January 5, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Keith E. Fogel, Jeehwan Kim, Jae-Woong Nah, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20150325650
    Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
    Type: Application
    Filed: July 8, 2015
    Publication date: November 12, 2015
    Inventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20150325682
    Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Inventors: CHENG-WEI CHENG, JACK O. CHU, DEVENDRA K. SADANA, KUEN-TING SHIU, YANNING SUN
  • Publication number: 20150311179
    Abstract: A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.
    Type: Application
    Filed: July 9, 2015
    Publication date: October 29, 2015
    Inventors: CHENG-WEI CHENG, SHU-JEN HAN, MASAHARU KOBAYASHI, KO-TAO LEE, DEVENDRA K. SADANA, KUEN-TING SHIU
  • Patent number: 9159822
    Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: October 13, 2015
    Assignee: International Business Machines Corporation
    Inventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20150287790
    Abstract: A semiconductor structure including a (100) silicon substrate having a plurality openings located within the silicon substrate, wherein each opening exposes a surface of the silicon substrate having a (111) crystal plane. This structure further includes an epitaxial semiconductor material located on an uppermost surface of the (100) silicon substrate, and a gallium nitride material located adjacent to the surface of the silicon substrate having the (111) crystal plane and adjacent a portion of the epitaxial semiconductor material. The structure also includes at least one semiconductor device located upon and within the gallium nitride material and at least one other semiconductor device located upon and within the epitaxial semiconductor material.
    Type: Application
    Filed: May 29, 2015
    Publication date: October 8, 2015
    Inventors: Can Bayram, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Publication number: 20150279696
    Abstract: The present invention provides ART techniques with reduced LER. In one aspect, a method of ART with reduced LER is provided which includes the steps of: providing a silicon layer separated from a substrate by a dielectric layer; patterning one or more ART lines in the silicon layer selective to the dielectric layer; contacting the silicon layer with an inert gas at a temperature, pressure and for a duration sufficient to cause re-distribution of silicon along sidewalls of the ART lines patterned in the silicon layer; using the resulting smoothened, patterned silicon layer to pattern ART trenches in the dielectric layer; and epitaxially growing a semiconductor material up from the substrate at the bottom of each of the ART trenches, to form fins in the ART trenches.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 1, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Guy Cohen, Katherine L. Saenger, Kuen-Ting Shiu
  • Publication number: 20150280023
    Abstract: A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.
    Type: Application
    Filed: May 27, 2015
    Publication date: October 1, 2015
    Inventors: CHRISTOS DIMITRAKOPOULOS, AUGUSTIN J. HONG, JEEHWAN KIM, DEVENDRA K. SADANA, KUEN-TING SHIU
  • Publication number: 20150262818
    Abstract: A method of forming a semiconductor substrate including a type III-V semiconductor material directly on a dielectric material that includes forming a trench in a dielectric layer, and forming a via within the trench extending from a base of the trench to an exposed upper surface of an underlying semiconductor including substrate. A III-V semiconductor material is formed extending from the exposed upper surface of the semiconductor substrate filling at least a portion of the trench.
    Type: Application
    Filed: March 12, 2014
    Publication date: September 17, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Edward W. Kiewra, Amlan Majumdar, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20150255460
    Abstract: Embodiments for the present invention provide a CMOS structure and methods for fabrication. In an embodiment of the present invention, a CMOS structure comprises a NFET, formed on a wafer, having a gate stack and a channel. A PFET having a gate stack and a channel is also formed on the wafer. The channel of the PFET and the channel of the NFET include semiconductor material formed on III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide because of a valence band offset between the semiconductor material and the III-V material. There is a height difference between a terminal of the NFET and a terminal of the PFET. In addition, the gate stack NFET is the same height as the gate stack PFET.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 10, 2015
    Applicant: International Business Machines Corporation
    Inventors: Cheng-wei Cheng, Amlan Majumdar, Kuen-Ting Shiu
  • Publication number: 20150255281
    Abstract: A method for forming a crystalline compound material on a single element substrate includes etching a high aspect ratio trench in a single element crystalline substrate and forming a dielectric layer over the substrate and on sidewalls and a bottom of the trench. The dielectric is removed from the bottom of the trench to expose the substrate at the bottom of the trench. A crystalline compound material is selectively grown on the substrate at the bottom of the trench.
    Type: Application
    Filed: May 22, 2015
    Publication date: September 10, 2015
    Inventors: Robert L. Bruce, Cheng-Wei Cheng, Joel P. de Souza, Ryan M. Martin, Uzma Rana, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 9123569
    Abstract: Embodiments for the present invention provide a CMOS structure and methods for fabrication. In an embodiment of the present invention, a CMOS structure comprises a NFET, formed on a wafer, having a gate stack and a channel. A PFET having a gate stack and a channel is also formed on the wafer. The channel of the PFET and the channel of the NFET include semiconductor material formed on III-V semiconductor material, such that the III-V semiconductor material acts like a buried oxide because of a valence band offset between the semiconductor material and the III-V material. There is a height difference between a terminal of the NFET and a terminal of the PFET. In addition, the gate stack NFET is the same height as the gate stack PFET.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: Cheng-wei Cheng, Amlan Majumdar, Kuen-Ting Shiu
  • Publication number: 20150243773
    Abstract: A method including forming a pair of inner spacers along a vertical sidewall of a gate trench, gate trench extending into a III-V compound semiconductor-containing heterostructure, forming a gate conductor within the gate trench, removing a portion of a first dielectric layer selective to the gate conductor and the pair of inner spacers, forming a pair of outer spacers adjacent to the pair of inner spacers, the outer spacers are in direct contact with and self-aligned to the inner spacers, and forming a pair of source-drain contacts within an uppermost layer of the III-V compound semiconductor-containing heterostructure, the pair of source-drain contacts are self-aligned to the pair of outer spacers such that an edge of each individual source-drain contact is aligned with an outside edge of each individual outer spacer.
    Type: Application
    Filed: February 24, 2014
    Publication date: August 27, 2015
    Applicant: International Business Machines Corporation
    Inventors: Anirban Basu, Amlan Majumdar, Kuen-Ting Shiu, Yanning Sun
  • Publication number: 20150235838
    Abstract: Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.
    Type: Application
    Filed: May 6, 2015
    Publication date: August 20, 2015
    Inventors: Can Bayram, Cheng-Wei Cheng, Tak H. Ning, Devendra K. Sadana, Kuen-Ting Shiu