Abstract: A stacked-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit, and a conductive unit. The capacitor unit includes a plurality of first stacked-type capacitors sequentially stacked on top of one another, and each first stacked-type capacitor has a first positive portion and a first negative portion. The package unit includes a package resin body for enclosing the capacitor unit. The conductive unit includes a first conductive terminal and a second conductive terminal. The first conductive terminal has a first embedded portion and a first exposed portion, and the second conductive terminal has a second embedded portion and a second exposed portion. An outermost one of first stacked-type capacitors has a plurality of first exposed soldering microgrooves formed on an outer surface thereof for contacting the package resin body. The instant disclosure further provides a method of manufacturing a stacked-type solid electrolytic capacitor package structure.

Abstract: A durable LED light engine includes a printed circuit board including LEDs mounted thereon positioned between a substantially U-shaped top enclosure and a bottom enclosure. Once assembled together, the combination of the substantially U-shaped top enclosure, the printed circuit board and the bottom enclosure are held together with a molding material.

Abstract: A semiconductor structure includes a first dielectric layer, a first conductive via, a partial landing pad, a second dielectric layer, and a second conductive via. The first conductive via is disposed in the first dielectric layer. The partial landing pad is disposed on the first conductive via and the first dielectric layer, in which the partial landing pad has a top surface and a bottom surface, and the top surface of the partial landing pad has a width greater than or substantially equal to that of the bottom surface of the partial landing pad. The second dielectric layer is disposed on the partial landing pad. The second conductive via is disposed in the second dielectric layer and electrically connected to the partial landing pad.

Abstract: An integrated circuit including a first transistor having a first gate dielectric layer with a first thickness. The integrated circuit also includes a second transistor having a second gate dielectric layer with a second thickness and the second transistor is configured to electrically connect to the first transistor. The integrated circuit also includes a third transistor having a third gate dielectric layer with a third thickness and the third transistor is configured to electrically connect to at least one of the first transistor or the second transistor. The first thickness, the second thickness and the third thickness of the integrated circuit are all different.

Abstract: A three-dimensional image sensing device includes a light source, a sensing module, and a signal processing module. The sensing module includes a pixel array, a control unit, and a light source driver. The light source generates flashing light with a K multiple of a frequency of flicker noise or a predetermined frequency. The pixel array samples the flashing light to generate a sampling result. The control unit executes an image processing on the sampling result to generate a spectrum. The light source driver drives the light source according to the K multiple of the frequency or the predetermined frequency. The signal processing module generates the K multiple of the frequency according to the spectrum, or outputs the predetermined frequency to the light source driver, and generates depth information according to a plurality of first images/a plurality of second images during turning-on/turning-off of the light source included in the sampling result.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.

Abstract: A high voltage transistor includes a substrate, a well which is disposed within the substrate, a gate disposed on the well, a gate dielectric layer disposed between the well and the gate, two drift regions respectively disposed in the well at two sides of the gate, two source/drain regions respectively disposed within each drift region, wherein a width of the gate dielectric layer is smaller than a width of the source/drain region, and two isolation elements respectively disposed within each drift region

Abstract: Provided is a semiconductor structure including a substrate, a first gate, a second gate, a third gate and an inter-gate dielectric layer. The substrate has a first area and a second area, and the first surface of the first area is lower than the second surface of the second area. The first gate is disposed on the first surface of the first area. The second gate includes metal and is disposed on the first gate. The inter-gate dielectric layer is disposed between the first and second gates. The third gate includes metal and is disposed on the second surface of the second area. A method of foaming a semiconductor structure is further provided.

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. A method of forming a memory device is further provided.

Abstract: A stacked-type solid electrolytic capacitor package structure includes a capacitor unit, a package unit, and a conductive unit. The capacitor unit includes a plurality of first stacked-type capacitors sequentially stacked on top of one another, and each first stacked-type capacitor has a first positive portion and a first negative portion. The package unit includes a package resin body for enclosing the capacitor unit. The conductive unit includes a first conductive terminal and a second conductive terminal. The first conductive terminal has a first embedded portion and a first exposed portion, and the second conductive terminal has a second embedded portion and a second exposed portion. An outermost one of first stacked-type capacitors has a plurality of first exposed soldering microgrooves formed on an outer surface thereof for contacting the package resin body. The instant disclosure further provides a method of manufacturing a stacked-type solid electrolytic capacitor package structure.

Abstract: A fishing light system includes: an alternating current power source, a power supply device electrically connected to the alternating current power source, and a light emitting diode fishing lamp electrically connected to the power supply device. The LED fishing lamp is used in combination with the power supply device which is capable of converting alternating current into a power supply which a voltage peak value and a voltage valley value. Since the power supply device is not needed to covert alternating current into direction current, there is no need for the power supply device to be equipped with a coil transformer, which consequently reduces the volume, weight and cost of the fishing light system of the present invention.

Abstract: A matrix arrangement stacked-type solid electrolytic capacitor package structure includes a lead frame component, a plurality of capacitor units, and a package unit. The lead frame component includes a plurality of conductive holders arranged in matrix arrangement and a connection frame connected to the conductive holders. Each conductive holder includes a first conductive terminal and a second conductive terminal. The capacitor units are respectively disposed on the conductive holders. Each capacitor unit includes a plurality of first stacked-type capacitors sequentially stacked on top of one another and electrically connected with each other. Each first stacked-type capacitor has a first positive portion electrically connected to the first conductive terminal of the corresponding conductive holder and a first negative portion electrically connected to the second conductive terminal of the corresponding conductive holder.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; using a first patterned mask to form a gate dielectric layer on the substrate; removing the first patterned mask; removing part of the gate dielectric layer; and forming a shallow trench isolation (STI) adjacent to two sides of the gate dielectric layer.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a source region, a drain region, a gate, and a dummy contact. The source region and the drain region are formed in the substrate. The gate is formed on the substrate and between the source region and the drain region. The dummy contact includes a plurality of dummy plugs formed on the substrate, wherein the dummy plugs have depths decreasing towards the drain region.

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract: A durable LED light engine includes an printed circuit board including LEDs mounted thereon positioned between a substantially U-shaped top enclosure and a bottom enclosure. Once assembled together using alignment holes and projections, the open spaces in the combination of the substantially U-shaped top enclosure, the printed circuit board and the bottom enclosure are filled with a plastic sealant. Once cooled, the plastic sealant holds the combination of the substantially U-shaped top enclosure, the printed circuit board and bottom enclosure together.

Abstract: A method for manufacturing a MOS transistor device includes following steps. A substrate including at least an isolation structure formed therein is provided. Next, a MOS transistor device is formed on the substrate, the MOS transistor device includes a gate, a source region, a drain region and a spacer. After forming the MOS transistor device, at least a first dummy contact is formed on a drain side of the gate and a gate contact is formed to be electrically connected to the gate. The first dummy contact is spaced apart from a surface of the substrate and electrically connected to the gate contact.

Abstract: A high voltage metal-oxide-semiconductor transistor device having stepped gate structure and a manufacturing method thereof are provided. The manufacturing method includes following steps. A gate structure is formed on a semiconductor substrate. The semiconductor substrate includes a first region and a second region disposed on a side of a first part of the gate structure and a side of a second part of the gate structure respectively. A patterned mask layer is formed on the semiconductor substrate and the gate structure. The patterned mask layer covers the first region and the first part. The second part is uncovered by the patterned mask layer. An implantation process is performed to form a drift region in the second region. An etching process is performed to remove a part of the second part uncovered by the patterned mask layer. A thickness of the second part is less than that of the first part after the etching process.

Abstract: Disclosed herein is a method of processing a device, comprising providing a substrate having a buffer layer disposed on a back side and forming an outer protection layer over the back side of the buffer layer, forming a thermal layer on the back side of the outer protection layer and heating the substrate through the thermal layer and the back side of the outer protective layer. A back side protection layer may be formed on the back side of the buffer layer. The thermal layer has a thermal emissivity coefficient of about 0.7 or greater and a thickness greater than a roughness of the back side of the outer protection layer. The back side protection layer is an oxide with a thickness between about 20 angstroms and about 50 angstroms. The outer protection layer is a nitride with a thickness between about 50 angstroms and about 300 angstroms.

Abstract: A method for manufacturing a MOS transistor device includes following steps. A substrate including at least an isolation structure formed therein is provided. Next, a MOS transistor device is formed on the substrate, the MOS transistor device includes a gate, a source region, a drain region and a spacer. After forming the MOS transistor device, at least a first dummy contact is formed on a drain side of the gate and a gate contact is formed to be electrically connected to the gate. The first dummy contact is spaced apart from a surface of the substrate and electrically connected to the gate contact.