Patents by Inventor Kun Lin

Kun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160340874
    Abstract: A position restoring and water splitting shower arm and a method of implementing the same. The shower arm comprises: a tube body and a switch valve. The tube body is provided with a water input port and a first water output port, while a second water output port is disposed on a middle section of the tube body. The switch valve is disposed vertically in the tube body, to switch connection and communication between the water input port and a first water output port, or between the water input port and the second water output port. The switch valve includes a valve seat; and a gravitation valve core disposed in the valve seat, with its one end provided with a valve core head, used to block the second water output port or the valve seat upper port.
    Type: Application
    Filed: May 16, 2016
    Publication date: November 24, 2016
    Inventors: Yuan-shan Liang, Wen-Kun Lin, Sheng-chao Dai
  • Publication number: 20160340876
    Abstract: A front-knob type multi-function shower arm and method of implementing the same. The method includes the following two water output modes: (1) a shower head water output mode: when rotating upward a knob on a front face, a three-way splitter is brought to connect a water input channel of a main body to a shower head water output channel, so that water flows to the shower head water output channel, and then it flows directly out from a shower head; and (2) a shower water output mode: when rotating downward a knob on a front face, the three-way splitter is brought to connect the water input channel of the main body to the shower water output channel, so that water flows to the shower water output channel, and then it flows out a shower from an outside connected shower hose.
    Type: Application
    Filed: May 6, 2016
    Publication date: November 24, 2016
    Inventors: Wen-kun Lin, Yuan-shan Liang, Sheng-chao Dai
  • Patent number: 9501602
    Abstract: In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Nitesh Katta, Jerry Chang-Jui Kao, Chin-Shen Lin, Yi-Chuin Tsai, Chou-Kun Lin, Kuo-Nan Yang, Chung-Hsing Wang
  • Publication number: 20160303639
    Abstract: A fastening angle bar molding method includes: providing a molding material piece having a through hole; providing a first mold having a protruding portion; providing a second mold having a dented portion which matches the protruding portion of the first mold to form a compressing space; placing the molding material piece between the first mold and the second mold, allowing the first mold and the second mold to engage with each other, pressing the protruding portion and the dented portion against each other to form the fastening angle bar, wherein the fastening angle bar has a first fastening portion, a second fastening portion defining an included angle with respect to the first fastening portion, and at least one angle reinforcing portion connected between the first fastening portion and the second fastening portion. A fastening angle bar is further provided.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 20, 2016
    Inventor: Jui-Kun LIN
  • Publication number: 20160295689
    Abstract: A flexible electronic module including a patterned flexible substrate, a stretchable material layer, and at least one electronic device is provided. The patterned flexible substrate includes at least one distributed region, and the stretchable material layer connects the distributed region. The electronic device is disposed on at least one of the patterned flexible substrate and the stretchable material layer. A manufacturing method of the flexible electronic module is also provided.
    Type: Application
    Filed: December 30, 2015
    Publication date: October 6, 2016
    Inventors: Chih-Chia Chang, Ming-Huan Yang, Cheng-Chung Lee, Jia-Chong Ho, Chen-Chu Tsai, Kun-Lin Chuang
  • Publication number: 20160284603
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.
    Type: Application
    Filed: June 6, 2016
    Publication date: September 29, 2016
    Inventors: I-Fan Lin, YI-TANG LIN, CHENG-HUNG YEH, HSIEN-HSIN SEAN LEE, CHOU-KUN LIN
  • Publication number: 20160276538
    Abstract: A vertical light emitting diode (LED) assembly with current spreading material over one or more sidewalls of the LED is disclosed. In one embodiment, the vertical LED assembly includes an LED comprising a light emitting layer disposed between a first layer having a first conductivity type and a second layer have a second conductivity type. The vertical LED assembly further includes a substrate bonded to the LED and a first electrode disposed between the substrate and the LED and electrically coupled to the first layer of the LED. A second electrode is formed on a surface of the second layer of the LED opposite the first layer, and electrically coupled to the second layer. In one embodiment, the second electrode extends over one or more sidewalls of the LED. In one embodiment, the second electrode extends laterally beyond one or more sidewalls of the LED.
    Type: Application
    Filed: March 17, 2015
    Publication date: September 22, 2016
    Inventors: Wei Zhao, Chao-Kun Lin, Chih-Wei Chuang
  • Publication number: 20160276559
    Abstract: The present specification discloses a novel light emitting diode package having a package substrate with a light emitting layer bonded to the package substrate. Unlike conventional LED packages (such as those shown in FIGS. 1 and 2), the chip handling substrate typically located between the package substrate and the light emitting layer is not present. In addition, the LED package of the present specification may comprise an insulating layer formed on the package substrate and the light emitting layer. The LED package of the present specification may further comprise an interconnect metal formed on the insulating layer and the light emitting layer, wherein the interconnect metal electrically connects the light emitting layer to the package substrate.
    Type: Application
    Filed: March 18, 2015
    Publication date: September 22, 2016
    Inventors: Chih-Wei Chuang, Chao-Kun Lin, Kai Liu
  • Patent number: 9437924
    Abstract: An antenna structure includes a first radiating body and a second radiating body. The first radiating body includes a feed portion, a first ground portion, a first extending portion, a second extending portion, and a third extending portion. The feed portion is electronically connected to the first ground portion. The first extending portion is electronically connected to the feed portion. The second extending portion is perpendicularly connected between the first extending portion and the third extending portion. The second radiating body includes a second ground portion and a combining portion electronically connected to the second ground portion. The combining portion is spaced from the third extending portion.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: September 6, 2016
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Kun-Lin Sung, Yen-Hui Lin
  • Patent number: 9433987
    Abstract: A manufacturing method for a stage tube that has a first tubular segment and a second tubular segment bordering mutually having different diameters includes: taking a metal plate that has a first segment and a second segment bordering mutually and having a first width and a second width, respectively, the first width being defined between two first paired edges, and the two second width being defined between two second paired edges; forming the first and second segments so as to define a first edge interval; rolling up the first and second segments so that the two first paired edges are jointed together and form the first tubular segment, while the second segment is formed to define a second edge interval; and rolling up the second segment so that the two second paired edges are jointed and form the second tubular segment.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: September 6, 2016
    Inventor: Jui-Kun Lin
  • Patent number: 9437776
    Abstract: A light emitting diode comprising an epitaxial layer structure, a first electrode, and a second electrode. The first and second electrodes are separately disposed on the epitaxial layer structure, and the epitaxial layer structure has a root-means-square (RMS) roughness less than about 3 at a surface whereon the first electrode is formed.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: September 6, 2016
    Assignee: Toshiba Corporation
    Inventors: Chao-Kun Lin, Heng Liu
  • Publication number: 20160237997
    Abstract: A miniature pump includes a cylinder, a piston module, a driving module and a wall body. The cylinder has a first end and a second end opposite to each other along a direction. The piston module is accommodated in the cylinder. The piston module has at least one pumping chamber structure protruded towards the second end, and the pumping chamber structure is able to extend or retract along the direction. The driving module is located at the second end and connected to the pumping chamber structure, configured to drive the pumping chamber structure to extend or retract along the direction. The wall body at least partially surrounds a position of the pumping chamber structure near the first end, and is located between the cylinder and the pumping chamber structure.
    Type: Application
    Filed: March 30, 2015
    Publication date: August 18, 2016
    Inventor: Kun-Lin CHANG
  • Publication number: 20160239227
    Abstract: A data storage device includes a flash memory and a controller. The flash memory includes a plurality of dies, and each of the dies includes a first memory plane and a second memory plane, wherein each of the first memory plane and the second memory plane includes a plurality of physical pages. The controller retrieves data of a first physical page of the first memory plane and data of a second physical page of the second memory plane in response to a read command which is arranged to read a target page.
    Type: Application
    Filed: November 24, 2015
    Publication date: August 18, 2016
    Inventors: Chin-Chi Lin, Kun-Lin Ho
  • Publication number: 20160226371
    Abstract: A protection circuit applied to an alternating current (AC) power source includes a sample-and-hold unit, a detection unit, and a discharge signal generation unit. The sample-and-hold unit samples a peak value of a direct current (DC) voltage during each period of a corresponding AC voltage, wherein the AC power source provides the AC voltage. The detection unit generates a detection signal when the DC voltage crosses a reference voltage corresponding to the peak value. The discharge signal generation unit generates a count signal when the discharge signal generation unit does not receive the detection signal within a predetermined time of a period of the AC voltage, accumulates the count signal, and generates a discharge signal to a discharge unit when a number of accumulated count signals is greater than a predetermined value, wherein the discharge unit discharges an X capacitor according to the discharge signal.
    Type: Application
    Filed: February 1, 2016
    Publication date: August 4, 2016
    Inventors: Ming-Chang Tsou, Meng-Jen Tsai, Yu-Kun Lin
  • Patent number: 9405883
    Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Shen Lin, Jerry Chang-Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chi-Yeh Yu, Kuo-Nan Yang
  • Publication number: 20160197068
    Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.
    Type: Application
    Filed: March 15, 2016
    Publication date: July 7, 2016
    Inventors: Chien-Ju Chao, Chou-Kun Lin, Yi-Chuin Tsai, Yen-Hung Lin, Po-Hsiang Huang, Kuo-Nan Yang, Chung-Hsing Wang
  • Patent number: 9373623
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: June 21, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Fan Lin, Yi-Tang Lin, Cheng-Hung Yeh, Hsien-Hsin Sean Lee, Chou-Kun Lin
  • Patent number: 9373817
    Abstract: A substrate structure and a device employing the same are disclosed. An embodiment of the disclosure provides the substrate structure including a flexible substrate and a first barrier layer. The flexible substrate has a top surface, a side surface, and a bottom surface. The first barrier layer is disposed on and contacting the top surface of the flexible substrate, wherein the first barrier layer consists of Si, N, and Z atoms, wherein the Z atom is selected from a group of H, C, and O atoms, and wherein Si of the first barrier layer is present in an amount from 35 to 42 atom %, N of the first barrier layer is present in an amount from 10 to 52 atom %, and Z of the first barrier layer is present in an amount from 6 to 48 atom %.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: June 21, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Hsiao-Fen Wei, Kun-Lin Chuang
  • Publication number: 20160162619
    Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Patent number: D767904
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: October 4, 2016
    Assignee: Kae Sheng Industrial Co., Ltd.
    Inventor: Ping-Kun Lin