Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

Abstract: A portable wireless communication device includes a connector configured to charge the portable wireless communication device by electronically connecting a power source to the portable wireless communication device. The connector includes a plurality of pins, one of the pins configured to serve as a radiation portion of an antenna to receive/send wireless signals when the connector electronically is uncoupled to the power source.

Abstract: A eutectic metal layer (e.g., gold/tin) bonds a carrier wafer structure to a device wafer structure. In one example, the device wafer structure includes a silicon substrate upon which an epitaxial LED structure is disposed. A layer of silver is disposed on the epitaxial LED structure. The carrier wafer structure includes a conductive silicon substrate covered with an adhesion layer. A layer of non-reactive barrier metal (e.g., titanium) is provided between the silver layer and the eutectic metal to prevent metal from the eutectic layer (e.g., tin) from diffusing into the silver during wafer bonding. During wafer bonding, the wafer structures are pressed together and maintained at more than 280° C. for more than one minute. Use of the non-reactive barrier metal layer allows the total amount of expensive platinum used in the manufacture of a vertical blue LED manufactured on silicon to be reduced, thereby reducing LED manufacturing cost.

Abstract: The present disclosure provides a novel light-emitting diode package and corresponding fabrication method for making such a package. The novel LED package comprises a resin carrier layer having a first and second surface. Embedded in the resin carrier layer are at least one electrical conductor and at least one LED. The embedded LED comprises a substrate having a bottom surface that is substantially exposed at the second surface of the resin carrier layer. The embedded LED further comprises a light emitting layer that is substantially exposed at the first surface of the resin carrier layer.

Abstract: A light-emitting device includes first and second semiconductor layers and a light-emitting layer between the first and second semiconductor layers. The light-emitting device also includes an improved electrode structures.

Abstract: An LED package and method for LED packaging is disclosed. In one embodiment, an LED package includes a carrier substrate having a predefined surface area, an LED device bonded to the carrier substrate, the LED device having a footprint area of at least fifty percent of the predefined surface area of the carrier substrate, and an encapsulant lens having a top surface inclined inwardly at an angle in the range of about 10° to about 140°. In one embodiment, the top surface of the encapsulant lens layer has a concave cone shape. In one embodiment, a wafer level packaging process includes forming an encapsulant lens layer portion having a top surface inclined inwardly at an angle in the range of about 10° to about 140° on each of a plurality of LED devices bonded to a carrier substrate wafer.

Abstract: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling layer is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling layer is formed by roughening a buffer layer of the light emitting device. The light emitting device includes an electrode in electrical communication with one of the first layer and the second layer through a portion of the light coupling layer.

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

Abstract: A light emitting diode (LED) assembly with a current blocking layer along the periphery of the LED is disclosed. In one embodiment, the LED assembly includes an LED comprising a light emitting layer disposed between a first layer having a first conductivity type and a second layer having a second conductivity type. The LED assembly further includes a contact electrically coupled to the first layer and a current blocking layer formed along a periphery of the LED at an interface with the contact, and covering a peripheral portion of the first contact. The current blocking layer forms a non-ohmic connection with the contact, thereby limiting the current injection between the contact and the first layer of the LED. In one embodiment, the current blocking layer surrounds a portion of the first layer, defining a portion of the light emitting layer that emits photons. In one embodiment, the current blocking layer comprises a transparent insulating layer between the LED and the contact.

Abstract: A door closer has a fixing set, a bidirectional set and an extending set. The fixing set has an elongated tube. The elongated tube has two opposite sidewalls and an opening. The bidirectional set is connected to the fixing set, is movably mounted in the elongated tube and has a connecting panel formed on and protruding from the bidirectional set and extending out of the opening. The extending set is pivotally connected to the bidirectional set and has a guiding track, an extending arm, a locking board and a connecting panel. The extending arm is movably mounted in the guiding track and has a connecting end extending out of the guiding track. The locking board engages the guiding track and is connected to the extending arm to adjust a total length of the extending set. The connecting panel is connected to the connecting end of the extending arm.

Abstract: An embodiment cell shift scheme includes abutting a first transistor cell against a second transistor cell and shifting a place and route boundary away from a polysilicon disposed between the first transistor cell and the second transistor cell. In an embodiment, the cell shift scheme includes shifting the place and route boundary to prevent a mismatch between a layout versus schematic (LVS) netlist and a post-simulation netlist.

Abstract: A substrate structure and a device employing the same are disclosed. An embodiment of the disclosure provides the substrate structure including a flexible substrate and a first barrier layer. The flexible substrate has a top surface, a side surface, and a bottom surface. The first barrier layer is disposed on and contacting the top surface of the flexible substrate, wherein the first barrier layer consists of Si, N, and Z atoms, wherein the Z atom is selected from a group of H, C, and 0 atoms, and wherein Si of the first barrier layer is present in an amount from 35 to 42 atom %, N of the first barrier layer is present in an amount from 10 to 52 atom %, and Z of the first barrier layer is present in an amount from 6 to 48 atom %.

Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.

Abstract: A flip-chip LED assembly with relief channel and a method for making the flip-chip LED assembly is disclosed. In one embodiment, the flip-chip LED assembly includes a flip-chip LED with a via and a channel formed in the surface of the flip-chip LED. The channel extends from the via to a sidewall of the flip-chip LED. In another embodiment, a plurality of vias and a plurality of channels are formed in the surface of the flip-chip LED. Each of the plurality of channels extend from each of the vias to another via, or to a sidewall of the flip-chip LED.

Abstract: A method for singulating a semiconductor device dies from a wafer, and a singulated semiconductor device die is disclosed. In one embodiment, the method includes forming a plurality of recesses in a surface of the wafer along the edges of the semiconductor device dies to be singulated, each of the recesses having a tapered inner surface. The method further includes applying pressure to an opposite surface of the wafer along the edges of the semiconductor device dies, separating the edges of the semiconductor device dies from the wafer. In one embodiment, the recesses are formed by a pulsed laser. In one embodiment, the pressure is applied by a wafer breaking machine.

Abstract: A door closer has a fixing set, a bidirectional set and an extending set. The fixing set has an elongated tube. The elongated tube has two opposite sidewalls and an opening. The bidirectional set is connected to the fixing set, is movably mounted in the elongated tube and has a connecting panel formed on and protruding from the bidirectional set and extending out of the opening. The extending set is pivotally connected to the bidirectional set and has a guiding track, an extending arm, a locking board and a connecting panel. The extending arm is movably mounted in the guiding track and has a connecting end extending out of the guiding track. The locking board engages the guiding track and is connected to the extending arm to adjust a total length of the extending set. The connecting panel is connected to the connecting end of the extending arm.

Abstract: Embodiments of mechanisms for forming power gating cells and virtual power circuits on multiple active device layers are described in the current disclosure. Power gating cells and virtual power circuits are formed on separate active device layers to allow interconnect structure for connecting with the power source be formed on a separate level from the interconnect structure for connecting the power gating cells and the virtual power circuits. Such separation prevents these two types of interconnect structures from competing for the same space. Routings for both types of interconnect structures become easier. As a result, metal lengths of interconnect structures are reduced and the metal widths are increased. Reduced metal lengths and increased metal widths reduce resistance, improves resistance-capacitance (RC) delay and electrical performance, and improves interconnect reliability, such as reducing electro-migration.

Abstract: An in-mold vibratile injection compression molding method and molding apparatus thereof are described. While performing a filling stage, a first piezoelectric actuator and a second piezoelectric actuator are use to vibrate the molding material along at least two directions for precisely filling the molding material into the micro-structure by adjusting the filling flow velocity of the molding material associated with the proper molding material temperature and by maintaining a molding material temperature of a skin solidified layer in the cavity between a glass transition temperature and a melting temperature in order to avoid the form error, to increase the groove filling rate and to improve the residual stress.

Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.

Abstract: This invention provides a light-emitting chip device with high thermal conductivity, which includes an epitaxial chip, an electrode disposed on a top surface of the epitaxial chip and a U-shaped electrode base cooperating with the electrode to provide electric energy to the epitaxial chip for generating light by electric-optical effect. The epitaxial chip includes a substrate and an epitaxial-layer structure with a roughening top surface and a roughening bottom surface for improving light extracted out of the epitaxial chip. A thermal conductive transparent reflective layer is formed between the substrate and the epitaxial-layer structure. The electrode base surrounds the substrate, the transparent reflective layer and a first cladding layer of the epitaxial-layer structure to facilitate the dissipation of the internal waste heat generated when the epitaxial chip emitting light. A method for manufacturing the chip device of the present invention is provided.