Patents by Inventor Kun Lin

Kun Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9171926
    Abstract: An integrated circuit includes a first and a second standard cell. The first standard cell includes a first gate electrode, and a first channel region underlying the first gate electrode. The first channel region has a first channel doping concentration. The second standard cell includes a second gate electrode, and a second channel region underlying the second gate electrode. The second channel region has a second channel doping concentration. A dummy gate includes a first half and a second half in the first and the second standard cells, respectively. The first half and the second half are at the edges of the first and the second standard cells, respectively, and are abutted to each other. A dummy channel is overlapped by the dummy gate. The dummy channel has a third channel doping concentration substantially equal to a sum of the first channel doping concentration and the second channel doping concentration.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: October 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Publication number: 20150303359
    Abstract: An LED package and method for LED packaging is disclosed. In one embodiment, an LED package includes a carrier substrate having a predefined surface area, an LED device bonded to the carrier substrate, the LED device having a footprint area of at least fifty percent of the predefined surface area of the carrier substrate, and an encapsulant lens having a top surface inclined inwardly at an angle in the range of about 10° to about 140°. In one embodiment, the top surface of the encapsulant lens layer has a concave cone shape. In one embodiment, a wafer level packaging process includes forming an encapsulant lens layer portion having a top surface inclined inwardly at an angle in the range of about 10° to about 140° on each of a plurality of LED devices bonded to a carrier substrate wafer.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 22, 2015
    Applicant: TOSHIBA CORPORATION
    Inventors: Kai Liu, Chao-Kun Lin
  • Publication number: 20150302128
    Abstract: In some embodiments, in a method, placement of a design layout is performed. The design layout includes a power rail segment, several upper-level power lines and several cells. The upper-level power lines cross over and bound the power rail segment at where the upper-level power lines intersect with the power rail segment. The cells are powered through the power rail segment. For each cell, a respective current through the power rail segment during a respective SW of the cell is obtained. One or more groups of cells with overlapped SWs are determined. One or more EM usages of the power rail segment by the one or more groups of cells using the respective currents of each group of cells are obtained. The design layout is adjusted when any of the one or more EM usages of the power rail segment causes an EM susceptibility of the power rail segment.
    Type: Application
    Filed: April 17, 2014
    Publication date: October 22, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: NITESH KATTA, JERRY CHANG-JUI KAO, CHIN-SHEN LIN, YI-CHUIN TSAI, CHOU-KUN LIN, KUO-NAN YANG, CHUNG-HSING WANG
  • Publication number: 20150303179
    Abstract: An LED assembly with an ESD protection device integrated into the carrier substrate and a method for making the LED assembly is disclosed. In one embodiment, the LED assembly includes an LED in contact with a bonding layer in contact with a substrate. The substrate has a region containing a circuit element. The bonding layer forms an ohmic connection between the region containing the circuit element and the LED. In one embodiment, the region containing the circuit element is an ESD protection device, such as a Zener diode.
    Type: Application
    Filed: April 18, 2014
    Publication date: October 22, 2015
    Applicant: TOSHIBA CORPORATION
    Inventors: Kai Liu, Chao-Kun Lin
  • Patent number: 9165882
    Abstract: A method is disclosed that includes the operations outlined below. A first criteria is determined to be met when directions of a first current and a second current around a first end and a second end of a metal segment respectively are opposite, in which the metal segment is a part of a power rail in at least one design file of a semiconductor device and is enclosed by only two terminal via arrays. A second criteria is determined to be met when a length of the metal segment is not larger than a electromigration critical length. The metal segment is included in the semiconductor device with a first current density limit depending on the length of the metal segment when the first and the second criteria are met.
    Type: Grant
    Filed: December 5, 2013
    Date of Patent: October 20, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Shen Lin, Jerry Chang-Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chi-Yeh Yu, Kuo-Nan Yang
  • Patent number: 9152751
    Abstract: A method is disclosed that includes the operations outlined below. An effective current pulse width of a maximum peak is determined based on a waveform function of a current having multiple peaks within a waveform period in a metal segment of a metal line in at least one design file of a semiconductor device to compute a duty ratio between the effective current pulse width and the waveform period. A maximum direct current limit of the metal segment is determined according to physical characteristics of the metal segment. An alternating current electromigration (AC EM) current limit is determined according to a ratio between the maximum direct current limit and a function of the duty ratio. The metal segment is included with the physical characteristics in the at least one design file when the maximum peak of the current does not exceed the AC EM current limit.
    Type: Grant
    Filed: May 1, 2014
    Date of Patent: October 6, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Shen Lin, Jerry Chang-Jui Kao, Nitesh Katta, Chou-Kun Lin, Yi-Chuin Tsai, Chien-Ju Chao, Kuo-Nan Yang
  • Patent number: 9142743
    Abstract: A vertical GaN-based LED is made by growing an epitaxial LED structure on a silicon wafer. A silver layer is added and annealed to withstand >450° C. temperatures. A barrier layer (e.g., Ni/Ti) is provided that is effective for five minutes at >450° C. at preventing bond metal from diffusing into the silver. The resulting device wafer structure is then wafer bonded to a carrier wafer structure using a high temperature bond metal (e.g., AlGe) that melts at >380° C. After wafer bonding, the silicon is removed, gold-free electrodes (e.g., Al) are added, and the structure is singulated. High temperature solder (e.g., ZnAl) that is compatible with the electrode metal is used for die attach. Die attach occurs at >380° C. for ten seconds without melting the bond metal or otherwise damaging the device. The entire LED contains no gold, and consequently is manufacturable in a high-volume gold-free semiconductor fabrication facility.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: September 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chih-Wei Chuang, Chao-Kun Lin, Long Yang, Norihito Hamaguchi
  • Patent number: 9142742
    Abstract: A thin-film light emitting diode includes an insulating substrate, a reflective metal electrode on the insulating substrate forming a current spreading layer, and an epitaxial structure on the electrode.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: September 22, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Chao-Kun Lin
  • Publication number: 20150231864
    Abstract: A composite plate structure including a flexible substrate and a release layer is provided. The flexible substrate has an upper surface and a lower surface. The release layer is disposed on the lower surface of the flexible substrate, and includes a hydrophobic material and a bonding material. The hydrophobic material includes at least one fluorine atom. The bonding material at least includes an amide functional group or an epoxy functional group. The bonding material is bonded to the flexible substrate through the amide functional group or the epoxy functional group. A flexible apparatus including the composite plate structure is also provided.
    Type: Application
    Filed: February 17, 2015
    Publication date: August 20, 2015
    Inventors: Hsiao-Fen Wei, Kun-Lin Chuang
  • Patent number: 9091260
    Abstract: A miniature pump includes a driving unit and an airflow control unit, which includes a bladder supporter, a compression unit, a valve base and an output valve. The compression unit has multiple intake valves and multiple bladders, each intake valve covers the corresponding intake through hole, each intake through hole is surrounded by a circular wall, wherein the circular wall is disposed on a bottom surface of the corresponding intake valve or a top surface of the corresponding bladder supporter. The valve base is arranged over the compression unit, and the valve base has multiple output through holes aligned with the bladders respectively. When the bladder is compressed, air inside the bladder is output via the output through hole and the output valve. When the bladder is decompressed, external air is introduced into the bladder via the intake through hole and the intake valve.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: July 28, 2015
    Assignee: KOGE ELECTRONICS CO., LTD
    Inventor: Kun-Lin Chang
  • Patent number: 9083079
    Abstract: A wireless local area network adapter includes a housing, a printed circuit board, an antenna, at least one elastic sheet and a plug. The printed circuit board includes a first ground plane. The antenna is electronically connected to the first ground plane. The elastic sheet is positioned on the printed circuit board, and is electronically connected to the first ground plane. The plug includes a shell, at least one part of the shell made of metal, the at least one elastic sheet contacting the metal part of the shell for electronically connecting the shell.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: July 14, 2015
    Assignee: Chi Mei Communication Systems, Inc.
    Inventors: Ting-Chih Tseng, Kun-Lin Sung
  • Publication number: 20150183897
    Abstract: A polyelectrolyte includes a first segment and a second segment, wherein the structure of the first segment is at least one of formula (1) and formula (2); the structure of the second segment is at least one of formula (3) and formula (4). The polyelectrolyte undergoes microphase separation to form a nanoscale ordered self-assembled microstructure.
    Type: Application
    Filed: December 27, 2014
    Publication date: July 2, 2015
    Inventors: Chung-Hsiang Chao, Li-Duan Tsai, Chia-Chen Fang, Chih-Ching Chang, Chi-Yang Chao, Kun-Lin Liu
  • Patent number: 9070833
    Abstract: An LED device includes a strip-shaped electrode, a strip-shaped current blocking structure and a plurality of distributed current blocking structures. The current blocking structures are formed of an insulating material such as silicon dioxide. The strip-shaped current blocking structure is located directly underneath the strip-shaped electrode. The plurality of current blocking structures may be disc shaped portions disposed in rows adjacent the strip-shaped current blocking structure. Distribution of the current blocking structures is such that current is prevented from concentrating in regions immediately adjacent the electrode, thereby facilitating uniform current flow into the active layer and facilitating uniform light generation in areas not underneath the electrode. In another aspect, current blocking structures are created by damaging regions of a p-GaN layer to form resistive regions.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: June 30, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Chih-Wei Chuang, Chao-Kun Lin
  • Publication number: 20150179648
    Abstract: Systems and methods are provided for fabricating a semiconductor structure including an inverter chain. An example semiconductor structure includes a first device layer, a second device layer, and one or more inter-layer connection structures. The first device layer is formed on a substrate and includes one or more first inverter structures. The second device layer is formed on the first device layer and includes one or more second inverter structures. The one or more inter-layer connection structures are configured to electrically connect to the first inverter structures and the second inverter structures.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Inventors: I-FAN LIN, YI-TANG LIN, CHENG-HUNG YEH, HSIEN-HSIN SEAN LEE, CHOU-KUN LIN
  • Publication number: 20150171264
    Abstract: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling layer is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling layer is formed by roughening a buffer layer of the light emitting device. The light emitting device includes an electrode in electrical communication with one of the first layer and the second layer through a portion of the light coupling layer.
    Type: Application
    Filed: February 23, 2015
    Publication date: June 18, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Li Yan, Chao-Kun Lin, Chih-Wei Chuang
  • Patent number: 9051664
    Abstract: The instant disclosure relates to a nanostructuring process for an ingot surface prior to the slicing operation. A surface treatment step is performed for at least one surface of the ingot in forming a nanostructure layer thereon. The nanostructure layer is capable of enhancing the mechanical strength of the ingot surface to reduce the chipping ratio of the wafer during slicing.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: June 9, 2015
    Assignee: Sino-American Silicon Products Inc.
    Inventors: Jiunn-Yih Chyan, Jian-Jhih Li, Kun-Lin Yang, Wen-Ching Hsu
  • Patent number: 9047433
    Abstract: A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Nan Yang, Chou-Kun Lin, Jerry Chang-Jui Kao, Yi-Chuin Tsai, Chien-Ju Chao, Chung-Hsing Wang
  • Patent number: 9048538
    Abstract: A wireless communication device includes a housing and an antenna assembly. The antenna assembly includes a base board, a feed member electronically connecting with the base board to carry an electrical current, and a radio member including a first radio portion, the first radio portion defining a first slot. The radiator couples with the feed member, inducing an electrical current in the first radio portion. The radio member is electronically connected to the base board through the metal housing, enabling the induced electrical current to flow through the first radio portion, the metal housing, and the base board to form a current loop. The induced electrical current flows through the first slot to excite a first resonance mode, enabling the antenna assembly to receive/transmit a first wireless signal.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: June 2, 2015
    Assignee: Chi Mei Communication Systems, Inc.
    Inventors: Kun-Lin Sung, Ting-Chih Tseng, Yen-Hui Lin
  • Publication number: 20150140505
    Abstract: A computer-aided positioning and navigation system for dental implant includes a computer system having built therein a dental implant planning software and providing a 3D digital human tissues model to create an implant navigation information, a positioning assistive device including a body providing a positioning portion and a guide portion and a connection member carrying an optical positioning device, one or multiple optical capture devices, and a display device electrically connected to the computer system. The computer system controls the optical capture device to capture images and drives the display device to display a part of the content of the 3D digital human tissues model and the implant navigation information.
    Type: Application
    Filed: January 27, 2015
    Publication date: May 21, 2015
    Inventors: Hong-Tzong YAU, Yen-Kun LIN
  • Patent number: 9030365
    Abstract: A wireless communication device includes a metal housing, a baseboard, and a current feed member electronically connected to the baseboard to obtain an electrical current from the baseboard. The housing defines a first notch and a second notch communicating with the first notch. The housing couples with the current feed member, such that the first notch and the second notch both induce the electrical current to excite two resonance modes, the two resonance modes enabling the wireless communication device to receive and transmit first wireless signals and second wireless signals having different central frequencies.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: May 12, 2015
    Assignee: Chi Mei Communication Systems, Inc.
    Inventors: Kun-Lin Sung, Ting-Chih Tseng, Yen-Hui Lin