Patents by Inventor Kun Zhang

Kun Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250257624
    Abstract: A rapid assembly and automatic sampling drilling tool for frozen soil layer exploration includes a fixed flow divider, a flow guide pipe, a coring pipe and a drill bit. The fixed flow divider is connected to the drill bit through the flow guide pipe and the coring pipe mounted between the fixed flow divider and the drill bit. Two ends of the flow guide pipe communicate with the fixed flow divider and a main flow channel in the drill bit respectively. Hot water in the fixed flow divider can be conveyed into the drill bit through the flow guide pipe and sprayed from a nozzle arranged on the drill bit for drilling and coring operations. An inlet of the coring pipe communicates with a coring channel in an inner cavity in the drill bit, and a core sample drilled by the drill bit is taken out through the coring pipe.
    Type: Application
    Filed: May 17, 2023
    Publication date: August 14, 2025
    Inventors: An LIU, Zhigang SHAN, Jian WANG, Peng PENG, Kun ZHANG, Weida NI, Meifeng NIU
  • Patent number: 12388036
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: August 12, 2025
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Liang Chen, Wei Liu, Yanhong Wang, Zhiliang Xia, Wenxi Zhou, Kun Zhang, Yuancheng Yang
  • Patent number: 12388037
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: August 12, 2025
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yanhong Wang, Wei Liu, Liang Chen, Zhiliang Xia, Wenxi Zhou, Kun Zhang, Yuancheng Yang
  • Publication number: 20250243480
    Abstract: The invention provides scalable methods for measuring chromatin accessibility and RNA expression in the same single cells by connecting chromatin accessibility and transcriptome.
    Type: Application
    Filed: March 12, 2025
    Publication date: July 31, 2025
    Inventors: Kun Zhang, Song Chen
  • Publication number: 20250244900
    Abstract: A method for data deduplication of a storage apparatus and the storage apparatus are provided. In particular, a method for data deduplication of a storage apparatus, wherein the storage apparatus comprises a storage class memory (SCM) and a flash memory, the method comprising: obtaining a search result of searching for a fingerprint in fingerprint data stored in the SCM the fingerprint generated based on written data; and writing the written data to the flash memory in the case that the search result is the fingerprint generated based on the written data is not present in the fingerprint data.
    Type: Application
    Filed: April 24, 2024
    Publication date: July 31, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Kun ZHANG, Hao YAN
  • Publication number: 20250248032
    Abstract: A three-dimensional memory includes a stack structure including gate line layers and dielectric layers stacked alternatively in a first direction, an insulating structure extending through the stack structure in the first direction and including a first insulating portion extending through the stack structure, gate line slits including a first gate line slit extending through the stack structure in the first direction and extending along a second direction perpendicular to the first direction, wherein the first insulating portion comprises a sidewall connecting to the first gate line slit, and a semiconductor layer located at a side of the stack structure, wherein the first gate line slit is located at a side of the stack structure, and the first insulating portion extends through the semiconductor layer.
    Type: Application
    Filed: April 14, 2025
    Publication date: July 31, 2025
    Inventors: Zhong Zhang, Yuhui Han, Cuicui Kong, Kun Zhang
  • Patent number: 12367099
    Abstract: Example error correction methods and apparatus are described. In one example method, a register controller detects an error existing in a memory, and after detecting an uncorrected error (UCE), obtains a memory address in which the UCE occurs. The register controller reads raw data from a location indicated by the memory address, stores preset first data in the location indicated by the memory address, and reads second data from the location after storing the first data in the location. The register controller compares the first data with the second data to determine a first failure location in the location, determines raw data stored in the first failure location from the raw data in the location, and performs error correction on the raw data stored in the first failure location.
    Type: Grant
    Filed: June 1, 2023
    Date of Patent: July 22, 2025
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuwei Li, Xu Zhang, Wei Li, Kun Zhang, Wen Yin
  • Patent number: 12369317
    Abstract: A method for forming a 3D memory device is provided. The method comprises forming an array wafer including a core array region, a staircase region, and a periphery region. Forming the array wafer includes forming an alternating dielectric stack on a first substrate, forming a plurality of channel structures in the alternating dielectric stack in the core array region, each channel structure including a functional layer and a channel layer, forming a staircase structure in the staircase region, and forming a plurality of dummy channel structures. The method further comprises bonding a CMOS wafer to the array wafer; and removing the first substrate; removing a portion of functional layer of each channel structure to expose channel layer, and doping the exposed portion of the channel layer.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: July 22, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Kun Zhang
  • Publication number: 20250227928
    Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers along a first direction, a semiconductor layer over the stack structure, and a channel structure extending through the stack structure and in contact with the semiconductor layer. The channel structure includes a semiconductor channel extending along the first direction and a composite dielectric film surrounding the semiconductor channel. The semiconductor channel includes a first portion extending through at least one of the conductive layers. The at least one of the conductive layers is between the semiconductor layer and another of the conductive layers. The first portion includes a doped portion.
    Type: Application
    Filed: March 31, 2025
    Publication date: July 10, 2025
    Inventors: Kun Zhang, Wenxi Zhou, Zhiliang Xia
  • Publication number: 20250218697
    Abstract: The present invention provides an electrode material capable of realizing a lithium ion capacitor having high capacity and also excellent durability, and an electrode and a capacitor using the electrode material. An electrode is formed using an electrode material containing a composite 10 of graphene and carbon nanotubes, the composite having a ratio of carbon atoms to oxygen atoms (C/O) of 7 or more as measured by X-ray photoelectron spectroscopy and a carbon nanotube content of less than 20 mass % (excluding 0 mass %), and the electrode is used, for example, as a positive electrode to constitute a lithium ion capacitor.
    Type: Application
    Filed: May 18, 2023
    Publication date: July 3, 2025
    Inventors: Kun ZHANG, Hang YIN, Yukinori HATO
  • Publication number: 20250220908
    Abstract: In an example, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending vertically through the memory stack, a semiconductor layer over the memory stack and electrically connected to the channel structure, and a source contact over the memory stack and electrically connected to the semiconductor layer. The source contact and the memory stack are disposed on opposite sides of the semiconductor layer.
    Type: Application
    Filed: March 14, 2025
    Publication date: July 3, 2025
    Inventors: Kun Zhang, Zhong Zhang, Lei Liu, Wenxi Zhou, Zhiliang Xia
  • Patent number: 12345665
    Abstract: A calculation method for fractal dimensions of shale pores includes steps as follows. S1: multiple shale samples from a target stratum of a study area are obtained, parameter values of geological parameters of each of the multiple shale samples are obtained, followed by dividing the multiple shale samples into target shale samples and experimental shale samples. S2: PCA is performed on the parameter values to obtain principal components representing a variation of the geological parameters. fractal dimensions are calculated based on an existing fractal dimension calculation method. S3: the principal components are used as independent variables and the fractal dimensions are used as dependent variables, followed by performing regression analysis to obtain a quantitative calculation model. S4: the fractal dimensions of the target shale sample are calculated according to the parameter values and the quantitative calculation model for the fractal dimension based on the parameter values.
    Type: Grant
    Filed: December 20, 2024
    Date of Patent: July 1, 2025
    Assignees: SOUTHWEST PETROLEUM UNIVERSITY, CHINA UNIVERSITY OF GEOSCIENCES, WUHAN, JIANGXI PROVINCIAL SHALE GAS. INVESTMENT COMPANY, LTD
    Inventors: Xinyang He, Kun Zhang, Shu Jiang, Hulin Niu, Weiwei Liu, Songyang Wan, Chengzao Jia, Yan Song, Xiong Ding, Xueying Wang, Yi Shu, Tianyou Zhi, Daiyu Wu, Sihong Cheng, Yongjun Li, Yiting Qiao, Yi Zhang, Jiayi Liu, Lei Chen, Xuefei Yang, Fengli Han, Weishi Tang, Jingru Ruan, Hengfeng Gou, Yi Xiao, Lintao Li, Yipeng Liu, Ping Liu, Zeyun Wang, Laiting Ye, Meijia Wu, Lu Lu
  • Publication number: 20250212407
    Abstract: A three-dimensional (3D) memory device includes a first region and a second region arranged along a first direction, a stack structure including interleaved conductive layers and dielectric layers along a second direction perpendicular to the first direction, a semiconductor layer located on a side of the stack structure along the second direction, a source contact structure at a first side of the semiconductor layer opposite to the stack structure, wherein the source contact structure is in contact with the semiconductor layer, a peripheral circuit at a second side of the semiconductor layer opposite to the first side of the semiconductor layer, and a supporting structure located in the second region and extending through the semiconductor layer along the second direction, wherein a material of the supporting structure is different from a material of the semiconductor layer.
    Type: Application
    Filed: March 12, 2025
    Publication date: June 26, 2025
    Inventors: Cuicui Kong, Zhong Zhang, Linchun Wu, Kun Zhang, Wenxi Zhou
  • Patent number: 12338732
    Abstract: A quantitative prediction method for gas content of deep marine shale includes: obtaining raw data of known wells; establishing relationship formulas between pore specific surface areas and adsorbed gas contents of a known well in an area as an adsorbed gas content quantitative prediction model; establishing relationship formulas between pore volumes and free gas contents of the known well as a free gas content quantitative prediction model; summing the adsorbed gas contents and corresponding free gas contents to obtain total gas contents; calculating adsorbed gas contents, free gas contents and total gas contents of the known wells; drawing a predicted adsorbed gas content contour map, a predicted free gas content contour map and a predicted total gas content contour map; and reading an adsorbed gas content, a free gas content and a total gas content of an unknown well in the area from the above contour maps.
    Type: Grant
    Filed: October 17, 2024
    Date of Patent: June 24, 2025
    Assignees: Southwest Petroleum University, Sinopec Southwest Petroleum Bureau Co., Ltd, PetroChina Zhejiang Oilfield Company
    Inventors: Xinyang He, Kun Zhang, Hulin Niu, Chengzao Jia, Yan Song, Zhenxue Jiang, Shu Jiang, Xueying Wang, Nanxi Zhang, Xiaoxia Dong, Jun Dong, Ruisong Li, Tong Wang, Pu Huang, Jiasui Ouyang, Xingmeng Wang, Shoucheng Xu, Hanbing Zhang, Yubing Ji, Lei Chen, Xuefei Yang, Fengli Han, Weishi Tang, Jingru Ruan, Hengfeng Gou, Lintao Li, Yipeng Liu, Ping Liu
  • Patent number: 12338461
    Abstract: A three-dimensional culture method for large-scale preparation of stem cells, comprising a three-dimensional microcarrier-based cell resuscitation method, a three-dimensional microcarrier cell culture-based in situ passage method, a three-dimensional microcarrier in situ freeze preservation method for cells, a three-dimensional microcarrier cell adsorption culture method, a method for harvesting cells on a three-dimensional microcarrier, a method for sampling cells cultured on a microcarrier, and a three-dimensional microcarrier-based cell large-scale expansion method.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: June 24, 2025
    Assignee: Beijing CytoNiche Biotechnology Co., Ltd.
    Inventors: Xiaojun Yan, Wei Liu, Kun Zhang
  • Patent number: 12339270
    Abstract: A neural network-based water quality monitoring device for a marine ranch includes a floating board and a host computer monitor. The host computer monitor is disposed on a top of the floating board, and the host computer monitor is provided with a water quality monitoring system, and the water quality monitoring system is configured to collect water quality parameters of the marine ranch and analyze collected water quality parameters. The environmental monitoring unit is configured to use a hyperspectral water quality multiparameter monitor to monitor continuous spectral segments within a target wavelength range in water body in the marine ranch to monitor in real time data including a concentration of dissolved substances in the water, growth of algae, water pollution, water color, and presence of solid floating objects on water surface. The device can apply multiple water quality tests to improve the effectiveness and accuracy of water quality monitoring.
    Type: Grant
    Filed: March 5, 2025
    Date of Patent: June 24, 2025
    Assignee: Guangdong Ocean University
    Inventors: Yunrong Yan, Kun Zhang, Chengqi Sun, Shoujun Zhang, Banglin Deng, Yin Sun, Wei Wang
  • Publication number: 20250201308
    Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.
    Type: Application
    Filed: March 5, 2025
    Publication date: June 19, 2025
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Linchun WU, Kun ZHANG, Wenxi ZHOU
  • Patent number: 12327592
    Abstract: A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.
    Type: Grant
    Filed: April 10, 2024
    Date of Patent: June 10, 2025
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: DongXue Zhao, Tao Yang, Yuancheng Yang, Lei Liu, Di Wang, Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20250185213
    Abstract: A thermal management system includes a first path, a second path, a third path, a fourth path, and a multi-way valve. A first port and a second port of the multi-way valve are respectively communicated with an inlet and an outlet of the first path. A third port and a fourth port are respectively communicated with an inlet and an outlet of the second path. A fifth port and a sixth port are respectively communicated with an inlet and an outlet of the third path, the third path includes a second liquid outlet and a second liquid inlet, and the second liquid outlet and the second liquid inlet are separately configured to connect to a second cold plate. A seventh port and an eighth port are respectively communicated with an inlet and an outlet of the fourth path, and the fourth path includes a heat exchanger.
    Type: Application
    Filed: November 15, 2024
    Publication date: June 5, 2025
    Applicant: Huawei Digital Power Technologies Co., Ltd.
    Inventors: Tao HUANG, Malin LI, Hao MENG, Zhengdao GUO, Huan LIU, Kun ZHANG
  • Patent number: 12322596
    Abstract: Methods for thermal treatment on a semiconductor device is disclosed. One method includes obtaining a pattern of a treatment area having amorphous silicon, aligning a laser beam with the treatment area, the laser beam in a focused laser spot having a spot area equal to or greater than the treatment area, and performing a laser anneal on the treatment area by emitting the laser beam towards the treatment area for a treatment period.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: June 3, 2025
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Kun Zhang, Lei Liu, Yuancheng Yang, Wenxi Zhou, Zhiliang Xia