Abstract: Disclosed herein is a conjugate comprising a targeting moiety and a proteolytic moiety. According to some embodiments of the present disclosure, the targeting moiety comprises the nucleic acid of SEQ ID NO: 1, and a first conjugating group; and the proteolytic moiety comprises a ligand of E3 ubiquitin ligase, and a second conjugating group. The targeting moiety is linked to the proteolytic moiety via a click reaction occurred between the first and second conjugating groups. Also disclosed herein are methods of treating diseases by using the instant conjugate.

Abstract: A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.

Abstract: The present disclosure provides a shield and an electronic assembly. The electronic assembly comprises a base plate and a chip located on the base plate.

Abstract: A three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer, channel structures extending vertically through the memory stack and into the second semiconductor layer, source contacts in contact with a second side of the second semiconductor layer opposite to the first side; and a backside interconnect layer over the second side of the second semiconductor layer and including interlayer dielectric (ILD) layers and a source line mesh on the ILD layers. The source contacts are distributed on a side of the source line mesh. The source contacts extend through the ILD layers and into the second semiconductor layer.

Abstract: This disclosure relates to methods, polynucleotides, vectors, viral particles, cells, and systems or the engineering of human tissues. One aspect of the disclosure relates to using lineage-specific miRNA binding molecules to bias tissue lineage. Another aspect of the disclosure relates to using lineage-specific transcription factor overexpression to bias tissue lineage.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit.

Abstract: A three-dimensional memory includes a stack structure, a dummy structure and a gate line slit. The stack structure includes gate line layers and isolation layers stacked alternatively in the vertical direction. The dummy structure includes a first dummy section and a second dummy section. The gate line slit has one end extending into a gap formed by at least one of the first dummy section or the second dummy section. At least one of the first dummy section and the second dummy section partially overlaps a projection of the gate line slit onto the horizontal plane to realize connection between the dummy structure and the gate line slit.

Abstract: Provided are a cathode material for sodium-ion batteries, a preparation method therefor, and an application thereof, and the preparation method comprises the following steps: (1) mixing a nickel source, a manganese source, and a magnesium source to obtain a ternary salt solution, adding the ternary salt solution, a precipitating agent, a complexing agent, a boron source solution, and an organic additive to a reaction vessel in parallel flow, and performing a reaction to obtain a B-doped radially-packed hydroxide precursor; and (2) mixing the B-doped radially-packed hydroxide precursor obtained in step (1) with a sodium source, and performing sintering treatment to obtain the cathode material for sodium-ion batteries.

Abstract: The present disclosure provides a baby carrier including a base; a leg section fixedly connected to the base; a backrest section pivotably connected to the base; and a guider configured for passage of a seat belt. The guider includes a first guider arranged in the leg section and a second guider arranged in the backrest section. The baby carrier according to the present disclosure can be securely bound by the seat belt and can be stabilized against a backrest of a vehicle seat.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, a doped semiconductor layer, and a channel structure extending through the stack structure and in contact with the doped semiconductor layer. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A part of the gate dielectric portion faces, along the first direction, one of the conductive layers that is closest to the doped semiconductor layer.

Abstract: Performance is improved. There is provided a negative electrode material for a battery, in which the negative electrode material includes carbon, sodium tungstate, and silicon particles 33 including silicon, and in the silicon particle 33, a ratio of the amount of Si in Si2p derived from elemental silicon to the amount of Si in Si2p derived from SiO2 in a surface layer when measured by X-ray photoelectron spectroscopy is 3 or more on an atomic concentration basis.

Abstract: A quantitative prediction method for gas content of deep marine shale includes: obtaining raw data of known wells; establishing relationship formulas between pore specific surface areas and adsorbed gas contents of a known well in an area as an adsorbed gas content quantitative prediction model; establishing relationship formulas between pore volumes and free gas contents of the known well as a free gas content quantitative prediction model; summing the adsorbed gas contents and corresponding free gas contents to obtain total gas contents; calculating adsorbed gas contents, free gas contents and total gas contents of the known wells; drawing a predicted adsorbed gas content contour map, a predicted free gas content contour map and a predicted total gas content contour map; and reading an adsorbed gas content, a free gas content and a total gas content of an unknown well in the area from the above contour maps.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes disposing an alternating dielectric stack over a substrate, wherein the alternating dielectric stack includes first dielectric layers and second dielectric layers alternatingly stacked on the substrate. The method also includes forming a channel structure penetrating through the alternating dielectric stack and extending into the substrate, wherein the channel structure includes a channel layer disposed on a sidewall of a memory film. The method further includes removing the substrate and a portion of the memory film that extends into the substrate to expose a portion of the channel layer; and disposing an array common source (ACS) on the exposed portion of the channel layer.

Abstract: The present application discloses a rolling lawn aerator, including a perforating device, where the perforating device is capable of rolling on a lawn so as to perforate and aerate the lawn. The perforating device includes a body assembly and a plurality of perforating assemblies, and the plurality of perforating assemblies are arranged in a circumferential direction of the body assembly; and each of the perforating assemblies includes a perforating pipe, and at least a part of a structure of the perforating pipe exceeds the body assembly in a radial direction of the body assembly.

Abstract: In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a semiconductor layer, a supporting structure, a spacer structure, and a contact structure. The memory stack includes interleaved conductive layers and dielectric layers and includes a staircase region in a plan view. The semiconductor layer is in contact with the memory stack. The supporting structure overlaps the staircase region of the memory stack and is coplanar with the semiconductor layer. The supporting structure includes a material other than a material of the semiconductor layer. The spacer structure is outside the memory stack and is coplanar with the supporting structure and the semiconductor layer. The contact structure extends vertically and is surrounded by the spacer structure.

Abstract: The invention provides scalable methods for measuring chromatin accessibility and RNA expression in the same single cells by connecting chromatin accessibility and transcriptome. Specifically, the disclosure provides a methods for concurrent characterization of gene expression levels and epigenetic landscape within a single cell comprising determining chromatin accessibility and RNA expression in the cell with a splint oligonucleotide.

Abstract: Embodiments of three-dimensional memory devices and fabricating methods thereof are disclosed. One disclosed method for forming a memory structure comprises: forming a bottom conductive layer on a substrate; forming a dielectric stack on the bottom conductive layer, the dielectric stack comprising a plurality of alternatively arranged first dielectric layers and second dielectric layers; forming an opening penetrating the dielectric stack and exposing the bottom conductive layer; forming a cap layer on a bottom of the opening; forming a cylindrical body and a top contact on the cap layer and in the opening; and replacing the plurality of second dielectric layers with conductive layers.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: Disclosed are a visualization grouting device for coal and rock fissures and a test method, a test device including a visualization fissure grouting box body, a box body bracket, a grouting device and a monitoring device. A bottom plate is divided into four identical areas, rubber cushion blocks with different specifications are arranged to simulate different fissure widths and tortuosity, artificial protolith thin film is pasted inside, and a grouting hole and a plurality of pressure measuring holes are arranged in the center of the upper top plate. In the present disclosure, the grouting process of fissures under different grouting conditions, such as different fissure widths, roughness, grouting resistance and tortuosity of pore channels can be simulated, the grouting under different fissure conditions can be simultaneously simulated, and the differences of different grouting diffusion forms can be clearly and intuitively analyzed and compared through the visualization box body.