Abstract: A data storage method includes: in response to a stream ID carried by an IO write request of a host satisfying a first preset condition, writing data corresponding to the IO write request into a first storage unit; and in response to the stream ID carried by the IO write request satisfying a second preset condition, writing the data corresponding to the IO write request into a second storage unit, wherein the stream ID indicates write latency requirement information of the data corresponding to the IO write request, wherein a data write latency indicated by the stream ID satisfying the first preset condition is less than the data write latency indicated by the stream ID satisfying the second preset condition, wherein a read and write performance of the first storage unit is higher than the read and write performance of the second storage unit.

Abstract: A method for edge passivation of crystalline silicon-based shingle cells, in which multiple crystalline silicon-based shingle cells are stacked to form a shingle cell group with cut edges thereof co-planar to form a to-be-passivated surface, and then the shingle cell group is placed in a fixing tooling to form a passivation unit. The passivation unit is conveyed by a conveying mechanism to an evaporation and annealing mechanism. A first source material is evaporated at 20-300° C. under vacuum in the evaporation and annealing mechanism to form a first gaseous source material, which is deposited on the to-be-passivated surface to form a first passivation layer. The shingle cell group with the first passivation layer is annealed at 100-350° C. A passivation device for implementing such method is further provided.

Abstract: In certain aspects, a memory device includes a memory structure including memory strings, a first peripheral circuit coupled to the memory structure and including a first transistor including a first gate dielectric layer, a first semiconductor layer in contact with the first transistor, a second peripheral circuit coupled to the memory structure and including a second transistor including a second gate dielectric layer, and a second semiconductor layer in contact with the second transistor. The memory strings are between the first semiconductor layer and the second semiconductor layer in a first direction. A thickness of the first gate dielectric layer is greater than a thickness of the second gate dielectric layer in the first direction.

Abstract: Disclosed are a class of compounds having a new structure as an ATR inhibitor, and a stereoisomer, an optical isomer, a pharmaceutical salt, a prodrug and a solvate thereof. An in-vitro enzyme inhibitory activity study shows that the compounds have a strong inhibitory effect on an ATR enzyme, and can be used as prospecting compounds for treating ATR-mediated diseases.

Abstract: A permeable pavement system including a permeable pavement composition and a related method are provided. The permeable pavement system includes a first layer of a permeable pavement composition including a quantity of a first permeable pavement material and a quantity of cured carbon fiber composite material (CCFCM) incorporated therewith, the first layer defining a first surface; and a second layer of a second permeable pavement material deposited over a substantial entirety of and covering the first surface of the first layer of the permeable pavement composition, wherein the first layer interfaces with the second layer to at least strengthen the permeable pavement system.

Abstract: A vapor source system based on vapor-liquid ejector supercharging combined with flash vaporization technology belongs to the technical fields of waste heat utilization and steam generation. The system comprises a vapor-liquid ejector, a flash vaporization tank and a intermediate heat exchanger, wherein the vapor-liquid ejector uses high-pressure steam to raise temperature and pressure of low-pressure water absorbed from the flash vaporization tank; the pressure-increased water is flashed into low-pressure saturated steam after entering the flash vaporization tank; the saturated water which is not flashed is collected at the bottom of the flash vaporization tank.

Abstract: A tungsten compound is appropriately disposed on a surface of carbon. The negative electrode material is a negative electrode material for a battery that includes amorphous carbon and sodium tungstate is attached on a surface on the amorphous carbon and provided on the surface of the amorphous carbon. The sodium tungstate may have at least one of a cubic crystal and a tetragonal crystal.

Abstract: A deep state space generative model is augmented with intervention prediction. The state space model provides a principled way to capture the interactions among observations, interventions, critical event occurrences, true states, and associated uncertainty. The state space model can include a discrete-time hazard rate model that provides flexible fitting of general survival time distributions. The state space model can output a joint prediction of event risk, observation and intervention trajectories based on patterns in temporal progressions, and correlations between past measurements and interventions.

Abstract: In an example, a three-dimensional (3D) memory device includes a stack structure including interleaved conductive layers and dielectric layers, a first semiconductor layer above the stack structure, a second semiconductor layer above the first semiconductor layer, channel structures extending vertically through the stack structure and the first semiconductor layer, and a source contact in contact with the second semiconductor layer.

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

Abstract: Described are devices, systems and methods for managing a supplemental brake control system in autonomous vehicles. In some aspects, a supplemental brake management system includes brake control hardware and software that operates with a sensing mechanism for determining the brake operational status and a control mechanism for activating the supplemental brake control in an autonomous vehicle, which can be implemented in addition to the vehicle's primary brake control system.

Abstract: Presented are methods and compositions for obtaining sequence information from one or more individual cells. The methods are useful for obtaining sequence information for a single nucleotide sequence, and for multiplex generation of sequence information from one or more individual cells.

Abstract: The present invention relates to the technical field of hydrogen fuel power generation, specifically a hydrogen fuel high-speed rotating magnetohydrodynamic power generation device. The device comprises a shaft portion, a cover plate portion, a thin plate portion and a combustion propelling portion. The device craftily utilizes hydrogen electrochemical reaction and direct combustion of unionized hydrogen to complete the hydrogen catalytic ionization reaction while providing jet thrust for rotation. Advantages are that it is more efficient than hydrogen fuel cells, has high power density, which is suitable for high-power and high-energy power needs, utilizes no key special components and does not require auxiliary systems such as heat dissipation, breaking limitations of proton exchange membrane on hydrogen fuel cells and low efficiency of a Carnot cycle on hydrogen internal combustion engines.

Abstract: The present disclosure discloses a child safety seat, which is for being installed on a vehicle seat. The child safety seat includes a base having an anchor part connected to the vehicle seat; a seat coupled to the base; a top rod fixed to the rear of the base; a tether assembly including a top tether and a tether fixing portion that are connected with each other, the top tether being connected with the top rod and the tether fixing portion being connected with the vehicle seat; and an alarm device including a switch which can be triggered when the top tether is tightened. The present disclosure also discloses a tether assembly and a support structure. The child safety seat can conveniently prompt that it is not correctly fixed, and can be conveniently fixed and adjusted, thereby improving the safety and riding comfort of the child safety seat.

Abstract: A method and apparatus for storing liquid gases, such as liquid hydrogen, is provided. The liquid gas container includes multiple layers of insulation to enable non-vacuum insulation to be utilized while reducing cryopumping. An inner insulation layer is formed of a material which as a closed-cell structure and is thick enough such that the temperature at an outer surface of the inner insulation layer is greater than the boiling point of a gas within the outer insulation layer. The outer insulation layer may have an open-cell structure for the insulation material.

Abstract: The present disclosure provides a three-dimensional (3D) memory. The 3D memory may include a stack structure including gate layers and dielectric layers disposed alternately. The stack structure may include a step structure including a plurality of staircase structures disposed in a first direction and having different heights in a second direction. The 3D memory may include a plurality of first stops disposed in the first direction and located on the plurality of steps of at least one of the staircase structures, with each of the plurality of first stops disposed on the corresponding step of the plurality of steps. The 3D memory may include a protection layer covering the step structure and the first stops. The 3D memory may include a plurality of contact posts each extending through the protection layer and the first stop and being connected with the gate layer in the step corresponding to the first stop.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second semiconductor layer.

Abstract: Disclosed in the present disclosure are a positive electrode material precursor and a positive electrode material and preparation methods therefor, and a sodium-ion battery. The positive electrode material precursor comprises an inner core and a shell wrapping the periphery of the inner core, wherein the inner core is NixFeyMn1-x-y(OH)2, where 0.2?x?0.7, and 0.2?y?0.5; the shell is MaMn1-a(OH)2, where M is nickel or iron, and 0.05?a?0.7; and both the inner core and the shell are formed by stacking flaky primary particles.

Abstract: A semiconductor device includes a first dielectric layer, a source layer at a first side of the first dielectric layer and in contact with the first dielectric layer, a second dielectric layer at a second side opposite to the first side of the first dielectric layer and in contact with the first dielectric layer, a source contact structure extending vertically through the second dielectric layer and the first dielectric layer, and extending into the source layer and without penetrating through the source layer, a stack including interleaved stack conductive layers and stack third dielectric layers, the source layer being located between the first dielectric layer and the stack in a vertical direction, a channel structure extending vertically through the stack and the source layer, and an insulating structure extending vertically through the stack into the source layer.