Abstract: A memory device can include channel structures in a first region. The memory device can also include a plurality of word line cavity structures in a second region abutting the first region. The plurality of word line cavity structures can extend along a first direction. Each of the word line cavity structures can include a first contact structure in a first side of the word line cavity structure along a second direction perpendicular to the first direction. Each of the word line cavity structures can also include a second contact structure in a second side of the word line cavity structure along the second direction. The second side can be opposite to the first side. Each of the word line cavity structures can further include a slit structure. The first contact structure and the second contact structure can be separated with the slit structure along the second direction.

Abstract: A three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer, channel structures extending vertically through the memory stack and into the second semiconductor layer, source contacts in contact with a second side of the second semiconductor layer opposite to the first side; and a backside interconnect layer over the second side of the second semiconductor layer and including interlayer dielectric (ILD) layers and a source line mesh on the ILD layers. The source contacts are distributed on a side of the source line mesh. The source contacts extend through the ILD layers and into the second semiconductor layer.

Abstract: A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.

Abstract: A system on wafer assembly structure and an assembly method thereof. The system on wafer assembly structure comprises: a wafer layer, a dielectric layer and a circuit board layer sequentially stacked, and each provided with a bonding region, a testing region and an alignment region, respectively, a first assembly, and a second assembly, wherein the first assembly is arranged on one side of the wafer layer far away from the dielectric layer, and comprises a bearing portion and at least one latch portion connected with each other, and the bearing portion is detachably connected with the wafer layer. The second assembly is at least partially arranged around the first assembly. The second assembly has a hole portion for accommodating a latch portion, and the inner diameter of the hole portion is larger than the outer diameter of the latch portion.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a stop layer, a polysilicon layer, a memory stack including interleaved stack conductive layers and stack dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and the polysilicon layer, stopping at the stop layer.

Abstract: The present invention provides a method for recovering valuable metals from waste lithium ion batteries. The method comprises: short-circuit discharging, dismantling, crushing, roasting, and screening on waste lithium ion batteries to obtain active electrode powders; using alkaline solution to wash the active electrode powders, then filtering to remove copper and aluminum; drying the activated electrode powder after alkaline washing treatment, mix the dried activated electrode powder with starch and concentrated sulfuric acid and stir evenly to obtain the mixed material; calcining the mixed material with controlling the atmosphere; taking out the product obtained from calcination and using deionized water to extract the leachate and leaching residue with valence metal ions, and then obtaining the leachate after filtering.

Abstract: Memory devices and methods for forming the same are disclosed. In certain aspects, a memory device includes a filling layer; a stack structure including interleaved conductive layers and dielectric layers; a channel structure extending through the stack structure and the filling layer. The channel structure includes a memory film and a semiconductor channel. The memory device also includes a doped semiconductor layer in contact with the semiconductor channel. The filling layer is between the doped semiconductor layer and the stack structure. The memory device further includes an insulating layer, and a source contact extending through the insulating layer and in contact with the doped semiconductor layer. The doped semiconductor layer is between the insulating layer and the filling layer.

Abstract: The present disclosure discloses a base assembly including a base; a sliding element telescopically arranged on the base; a supporting leg which is pivotably connected to the sliding element and extended and retracted along with the sliding element, and which has an unfolded position when in use and a folded position when not in use; and a supporting leg retractable structure, which actuates the sliding element and the supporting leg to move toward inside of the base together in response to pivoting the supporting leg from the unfolded position to the folded position.

Abstract: Understanding the complex effects of genetic perturbations on cellular state and fitness in human pluripotent stem cells (hPSCs) has been challenging using traditional pooled screening techniques which typically rely on unidimensional phenotypic readouts. Here, Applicants use barcoded open reading frame (ORF) overexpression libraries with a coupled single-cell RNA sequencing (scRNA-seq) and fitness screening approach, a technique we call SEUSS (ScalablE fUnctional Screening by Sequencing), to establish a comprehensive assaying platform. Using this system, Applicants perturbed hPSCs with a library of developmentally critical transcription factors (TFs), and assayed the impact of TF overexpression on fitness and transcriptomic cell state across multiple media conditions. Applicants further leveraged the versatility of the ORF library approach to systematically assay mutant gene libraries and also whole gene families.

Abstract: Techniques are described for determining weight distribution of a vehicle. A method of performing autonomous driving operation includes determining a vehicle weight distribution that values for each axle of the vehicle that describe weight or pressure applied on a respective axle. The values of the vehicle weight distribution are determined by removing at least one value that is outside a range of pre-determined values from a set of sensor values. The method further includes determining a driving-related operation of the vehicle weight distribution. For example, the driving-related operation may include determining a braking amount for each axle and/or determining a maximum steering angle to operate the vehicle. The method further includes controlling one or more subsystems in the vehicle via an instruction related to the driving-related operation. For example, transmitting the instruction to the one or more subsystems causes the vehicle to perform the driving-related operation.

Abstract: Disclosed herein is an aptamer-peptide conjugate comprising a penetrating moiety and an L-form ribonucleic acid (L-RNA) aptamer linked thereto. According to some embodiments of the present disclosure, the L-RNA aptamer has an alkyne group linked to its 5? end, and the penetrating moiety comprises a cell-penetrating peptide (CPP), a modified amino acid residue, and a first linker linking the modified amino acid residue to the CPP, in which the side chain of the modified amino acid residue has an azide group, so that the L-RNA aptamer is linked to the penetrating moiety via Cu(I)-catalyzed azide-alkyne cycloaddition (CuAAC) reaction.

Abstract: The present disclosure provides a fracturing fluid mixing equipment including a clear water supply system, at least two mixing systems, at least one powder tank, at least two powder conveying systems, a mixing tank, a feeding system and a power system. The clear water supply system has two parallel water supply paths which are connected to the mixing system and the mixing tank respectively. The powder conveying system is connected to the powder tank. There are same number of powder conveying systems and mixing systems which are connected in one-to-one correspondence. The mixing system is connected into the mixing tank. The feeding system adds powder by pneumatic conveying. The power system provides driving force by pure electric power and/or electro-hydraulic power. According to present disclosure, the power system can reduce fuel consumption and exhaust emissions.

Abstract: Provided is an analysis method for determining gas-bearing situation of an unknown shale reservoir, includes: S1, selecting a shale reservoir of a target interval of a place; and collecting data of parameters of cores of each of a known gas-bearing shale reservoir A and a known water-bearing shale reservoir B; S2, calculating average values of the parameters of each of the reservoirs A and B respectively; S3, calculating average differences of the parameters of each of the reservoirs; S4, calculating covariance values of the parameters of each of the reservoirs; S5, establishing, according to the covariance values, an equation group and resolving discriminant coefficients; S6, establishing a discriminant equation according to the discriminant coefficients and solving a discriminant index; and S7, obtaining values of parameters of cores of a sample of the unknown shale reservoir, calculating a discriminant value, and determining gas-bearing situation of the unknown shale reservoir.

Abstract: In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.

Abstract: An apparatus and method for parameter comprehensive monitoring and troubleshooting of power transformation and distribution are disclosed. The apparatus includes a data acquisition unit, an on-site CPU, a main CPU, an operation and maintenance control center, a UPS and an energy storage breaking mechanism. Each on-site CPU compares the relevant state values of equipment line collected by a data acquisition unit with a threshold set by fiber Bragg grating sensor nodes and sums up to a main CPU. The main CPU stores and display the relevant state values through a display screen. The node represents each distribution point. A link represents a data transmission path. An attached table displays all state parameters. A working state of the distribution equipment is determined according to a color of the node and the link.

Abstract: Provided is an analysis method for determining gas-bearing situation of an unknown shale reservoir, includes: S1, selecting a shale reservoir of a target interval of a place; and collecting data of parameters of cores of each of a known gas-bearing shale reservoir A and a known water-bearing shale reservoir B; S2, calculating average values of the parameters of each of the reservoirs A and B respectively; S3, calculating average differences of the parameters of each of the reservoirs; S4, calculating covariance values of the parameters of each of the reservoirs; S5, establishing, according to the covariance values, an equation group and resolving discriminant coefficients; S6, establishing a discriminant equation according to the discriminant coefficients and solving a discriminant index; and S7, obtaining values of parameters of cores of a sample of the unknown shale reservoir, calculating a discriminant value, and determining gas-bearing situation of the unknown shale reservoir.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers above the substrate, a plurality of channel structures each extending vertically through the memory stack, a semiconductor layer above and in contact with the plurality of channel structures, a plurality of source contacts above the memory stack and in contact with the semiconductor layer, a plurality of contacts through the semiconductor layer, and a backside interconnect layer above the semiconductor layer including a source line mesh in a plan view. The plurality of source contacts are distributed below and in contact with the source line mesh. A first set of the plurality of contacts are distributed below and in contact with the source line mesh.

Abstract: A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.