Abstract: Examples of the present disclosure provide a semiconductor device, a manufacturing method thereof, and a memory system. The semiconductor device comprises: a stacking structure comprising a memory array area and a first sealing area; and at least one circle of sealing structure in the first sealing area and surrounding the memory array area, wherein the sealing structure comprises a sealing ring body penetrating through the stacking structure and at least two circles of first dummy interconnection structures connected with the sealing ring body.

Abstract: The present application discloses a semiconductor device and a fabrication method thereof, and a memory and a memory system. At least one cleavage plane guide structure extending along a second direction is disposed in a first cutting region adjacent to a first device region in a first direction in the semiconductor device, the second direction intersects the first direction, and the cleavage plane guide structure includes a first portion and a second portion that extend along the second direction, and the second portion has higher cleavage plane passability than the first portion. As such, a chip can cleave according to a preset direction and portion when stealth dicing is performed on the chip.

Abstract: A response interaction system for intelligently interacting with a low-voltage user includes: a distribution network and system master station, an intelligent electric meter, a mobile APP, an intelligent interaction terminal, an intelligent gateway, and a low-voltage user load. In the process of the low-voltage user participating in the demand response, the distribution network and system master station publishes a demand response plan and a demand response notification through the mobile APP, the low-voltage user receives the demand response plan and the demand response notification through the mobile APP, the low-voltage user is connected to the intelligent interaction terminal through the mobile APP and controls a load to operate or not operate through the intelligent gateway, to perform the demand response task.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack comprising interleaved conductive layers and dielectric layers, a plurality of semiconductor layers contacted with each other and located adjacent to the memory stack, a plurality of channel structures each extending vertically through the memory stack and at least one of the semiconductor layers, a source contact in contact with at least one of the semiconductor layers, and a contact pad located on one side of the semiconductor layers that are away from the memory stack.

Abstract: A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer, a spacer structure through the conductive layer and in contact with the insulating layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer. The contact structure includes a first contact portion and a second contact portion in contact with each other.

Abstract: The present invention belongs to the technical field of antibacterial drugs, and discloses a pyrrolylacylpiperidylamine compound and use thereof. The present invention in particular relates to a pyrrolylacylpiperidylamine compound and a pharmaceutically acceptable salt thereof, and use thereof in the preparation of a medicament for resisting infections with bacteria, mycoplasma or chlamydia.

Abstract: A memory device can include channel structures in a first region. The memory device can also include a plurality of word line cavity structures in a second region abutting the first region. The plurality of word line cavity structures can extend along a first direction. Each of the word line cavity structures can include a first contact structure in a first side of the word line cavity structure along a second direction perpendicular to the first direction. Each of the word line cavity structures can also include a second contact structure in a second side of the word line cavity structure along the second direction. The second side can be opposite to the first side. Each of the word line cavity structures can further include a slit structure. The first contact structure and the second contact structure can be separated with the slit structure along the second direction.

Abstract: A three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers over a first side of a second semiconductor layer, channel structures extending vertically through the memory stack and into the second semiconductor layer, source contacts in contact with a second side of the second semiconductor layer opposite to the first side; and a backside interconnect layer over the second side of the second semiconductor layer and including interlayer dielectric (ILD) layers and a source line mesh on the ILD layers. The source contacts are distributed on a side of the source line mesh. The source contacts extend through the ILD layers and into the second semiconductor layer.

Abstract: A memory device includes a stack structure and a first beam structure. The memory device includes array regions and an intermediate region arranged between the array regions in a first lateral direction. The stack structure includes a first block and a second block arranged in a second lateral direction. Each of the first block and the second block includes a wall-structure region. In the intermediate region, the wall-structure regions of the first block and the second block are separated by a staircase structure. The first beam structure is located in the intermediate region and extends along the second lateral direction. The first beam structure is connected to the wall-structure regions of the first block and the second block. The first beam structure includes first dielectric layers and electrode layers that are alternately stacked.

Abstract: A system on wafer assembly structure and an assembly method thereof. The system on wafer assembly structure comprises: a wafer layer, a dielectric layer and a circuit board layer sequentially stacked, and each provided with a bonding region, a testing region and an alignment region, respectively, a first assembly, and a second assembly, wherein the first assembly is arranged on one side of the wafer layer far away from the dielectric layer, and comprises a bearing portion and at least one latch portion connected with each other, and the bearing portion is detachably connected with the wafer layer. The second assembly is at least partially arranged around the first assembly. The second assembly has a hole portion for accommodating a latch portion, and the inner diameter of the hole portion is larger than the outer diameter of the latch portion.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a stop layer, a polysilicon layer, a memory stack including interleaved stack conductive layers and stack dielectric layers, and a plurality of channel structures each extending vertically through the memory stack and the polysilicon layer, stopping at the stop layer.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, a third semiconductor structure, a first bonding interface between the first semiconductor structure and the second semiconductor structure, and a second bonding interface between the second semiconductor structure and the third semiconductor structure. The first semiconductor structure includes an array of NAND memory strings and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a first peripheral circuit of the array of NAND memory strings including a first transistor, and a second semiconductor layer in contact with the first transistor. A third semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a third semiconductor layer in contact with the second transistor.

Abstract: The present invention provides a method for recovering valuable metals from waste lithium ion batteries. The method comprises: short-circuit discharging, dismantling, crushing, roasting, and screening on waste lithium ion batteries to obtain active electrode powders; using alkaline solution to wash the active electrode powders, then filtering to remove copper and aluminum; drying the activated electrode powder after alkaline washing treatment, mix the dried activated electrode powder with starch and concentrated sulfuric acid and stir evenly to obtain the mixed material; calcining the mixed material with controlling the atmosphere; taking out the product obtained from calcination and using deionized water to extract the leachate and leaching residue with valence metal ions, and then obtaining the leachate after filtering.

Abstract: Understanding the complex effects of genetic perturbations on cellular state and fitness in human pluripotent stem cells (hPSCs) has been challenging using traditional pooled screening techniques which typically rely on unidimensional phenotypic readouts. Here, Applicants use barcoded open reading frame (ORF) overexpression libraries with a coupled single-cell RNA sequencing (scRNA-seq) and fitness screening approach, a technique we call SEUSS (ScalablE fUnctional Screening by Sequencing), to establish a comprehensive assaying platform. Using this system, Applicants perturbed hPSCs with a library of developmentally critical transcription factors (TFs), and assayed the impact of TF overexpression on fitness and transcriptomic cell state across multiple media conditions. Applicants further leveraged the versatility of the ORF library approach to systematically assay mutant gene libraries and also whole gene families.

Abstract: Memory devices and methods for forming the same are disclosed. In certain aspects, a memory device includes a filling layer; a stack structure including interleaved conductive layers and dielectric layers; a channel structure extending through the stack structure and the filling layer. The channel structure includes a memory film and a semiconductor channel. The memory device also includes a doped semiconductor layer in contact with the semiconductor channel. The filling layer is between the doped semiconductor layer and the stack structure. The memory device further includes an insulating layer, and a source contact extending through the insulating layer and in contact with the doped semiconductor layer. The doped semiconductor layer is between the insulating layer and the filling layer.

Abstract: The present disclosure discloses a base assembly including a base; a sliding element telescopically arranged on the base; a supporting leg which is pivotably connected to the sliding element and extended and retracted along with the sliding element, and which has an unfolded position when in use and a folded position when not in use; and a supporting leg retractable structure, which actuates the sliding element and the supporting leg to move toward inside of the base together in response to pivoting the supporting leg from the unfolded position to the folded position.

Abstract: Techniques are described for determining weight distribution of a vehicle. A method of performing autonomous driving operation includes determining a vehicle weight distribution that values for each axle of the vehicle that describe weight or pressure applied on a respective axle. The values of the vehicle weight distribution are determined by removing at least one value that is outside a range of pre-determined values from a set of sensor values. The method further includes determining a driving-related operation of the vehicle weight distribution. For example, the driving-related operation may include determining a braking amount for each axle and/or determining a maximum steering angle to operate the vehicle. The method further includes controlling one or more subsystems in the vehicle via an instruction related to the driving-related operation. For example, transmitting the instruction to the one or more subsystems causes the vehicle to perform the driving-related operation.

Abstract: Disclosed herein is an aptamer-peptide conjugate comprising a penetrating moiety and an L-form ribonucleic acid (L-RNA) aptamer linked thereto. According to some embodiments of the present disclosure, the L-RNA aptamer has an alkyne group linked to its 5? end, and the penetrating moiety comprises a cell-penetrating peptide (CPP), a modified amino acid residue, and a first linker linking the modified amino acid residue to the CPP, in which the side chain of the modified amino acid residue has an azide group, so that the L-RNA aptamer is linked to the penetrating moiety via Cu(I)-catalyzed azide-alkyne cycloaddition (CuAAC) reaction.

Abstract: Provided is an analysis method for determining gas-bearing situation of an unknown shale reservoir, includes: S1, selecting a shale reservoir of a target interval of a place; and collecting data of parameters of cores of each of a known gas-bearing shale reservoir A and a known water-bearing shale reservoir B; S2, calculating average values of the parameters of each of the reservoirs A and B respectively; S3, calculating average differences of the parameters of each of the reservoirs; S4, calculating covariance values of the parameters of each of the reservoirs; S5, establishing, according to the covariance values, an equation group and resolving discriminant coefficients; S6, establishing a discriminant equation according to the discriminant coefficients and solving a discriminant index; and S7, obtaining values of parameters of cores of a sample of the unknown shale reservoir, calculating a discriminant value, and determining gas-bearing situation of the unknown shale reservoir.