Abstract: Embodiments of three-dimensional (3D) memory devices and fabricating methods thereof are disclosed. A disclosed 3D memory device can comprise an alternating conductive/dielectric stack on a substrate, a plurality of channel structures in the alternating conductive/dielectric stack, and a plurality of gate line slit (GLS) structures in the alternating conductive/dielectric stack. Each GLS structure can include a plurality of first type GLS portions penetrating the alternating conductive/dielectric stack, and a plurality of second type GLS portions in an upper portion of the alternating conductive/dielectric stack.

Abstract: A method of fabricating a three-dimensional (3D) memory device includes forming a stack structure on a substrate, forming a channel structure, a dummy channel structure, and a gate line slit structure penetrating through the stack structure and extending into the substrate, removing the substrate to expose a first side of the stack structure, forming a protective layer covering an exposed portion of the channel structure on the first side of the stack structure, removing at least the exposed portion of the channel structure, and removing the protective layer after removing at least the exposed portion of the channel structure.

Abstract: The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes forming an alternating dielectric stack on a substrate, wherein the alternating dielectric stack includes a plurality of dielectric layer pairs, each dielectric layer pair comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer. The method also includes forming a staircase structure in the alternating dielectric stack and disposing an insulating layer on the staircase structure and the alternating dielectric stack. The method further includes forming an embedded hard mask on the insulating layer, wherein the embedded hard mask includes two or more sets of patterns configured to form two or more sets of vertical structures that are fabricated sequentially. The two or more sets of patterns are embedded in the 3D memory device.

Abstract: A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a first angled structure, and a first diameter of the memory film at the bottom portion below the first angled structure is smaller than a second diameter of the memory film at an upper portion above the first angled structure.

Abstract: A three-dimensional (3D) memory device includes a stack structure having interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure along a first direction. The channel structure is in contact with a source of the 3D memory device at a bottom portion of the channel structure. The channel structure includes a semiconductor channel, and a memory film over the semiconductor channel. The memory film includes a tunneling layer over the semiconductor channel, a storage layer over the tunneling layer, and a blocking layer over the storage layer. A first thickness of the bottom portion of the channel structure is larger than a second thickness of a top portion of the channel structure.

Abstract: Disclosed is a marine communication buoy. The marine communication buoy includes s a round seat, side slots and hollow boxes, four side slots are uniformly distributed outside the round seat, and each side slot is connected with the hollow box in a sliding way. The marine communication buoy also includes sealing rings and buckle covers, an outer part of each hollow box is provided with a sealing ring, an outer end of each hollow box is slidably connected with the buckle cover, and an inner side of the buckle cover is in contact with the sealing ring. The marine communication buoy also includes valves and connector pipes, the connector pipe is arranged at an outer side of each buckle cover, and the connector pipe is provided with the valve.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, an N-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the N-type doped semiconductor layer, and a source contact above the memory stack and in contact with the N-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the N-type doped semiconductor layer.

Abstract: An active common mode filter is configured to be positioned between a power supply and a switching converter-device/load for reducing common mode noise. The active common mode filter includes an active capacitor that has a sensing stage including one or more sensing capacitors, an amplifying stage including a common collector amplifier for mitigating an input voltage divider effect coupled to a common emitter amplifier for providing high gain, and an injection stage including one or more injection capacitors. Depending on the required attenuation in different applications, a multistage active common mode filter may be formed with a necessary number of stages, each stage including an active capacitor and an inductor.

Abstract: A memory stack including interleaved conductive layers and dielectric layers is formed by replacing, through a slit opening, sacrificial layers with conductive layers. A first source contact portion is formed in the slit opening. Simultaneously, a channel local contact opening is formed through a local dielectric layer to expose a channel structure, and a staircase local contact opening is formed through the local dielectric layer to expose one of the conductive layers at a staircase structure on an edge of the memory stack. Also, simultaneously, a channel local contact, a second source contact portion above a first source contact portion in the slit opening, and a staircase local contact are formed, respectively, in the channel local contact opening, the slit opening, and the staircase local contact opening.

Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

Abstract: A vapor source system based on vapor-liquid ejector supercharging combined with flash vaporization technology belongs to the technical fields of waste heat utilization and steam generation. The system comprises a vapor-liquid ejector, a flash vaporization tank and a intermediate heat exchanger, wherein the vapor-liquid ejector uses high-pressure steam to raise temperature and pressure of low-pressure water absorbed from the flash vaporization tank; the pressure-increased water is flashed into low-pressure saturated steam after entering the flash vaporization tank; the saturated water which is not flashed is collected at the bottom of the flash vaporization tank.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a P-type doped semiconductor layer above the memory stack, a plurality of channel structures each extending vertically through the memory stack into the P-type doped semiconductor layer, and a source contact above the memory stack and in contact with the P-type doped semiconductor layer. An upper end of each of the plurality of channel structures is flush with or below a top surface of the P-type doped semiconductor layer.

Abstract: The present disclosure relates to a high and low pressure manifold liquid supply system for fracturing units, including: a trailer, a high and low pressure manifold arranged on the trailer, a support frame arranged on a platform of the trailer, and a power distribution switch cabinet arranged on the support frame, which is configured to be electrically connected to the electrically-driven fracturing units and configured to distribute electricity to the electrically-driven fracturing units. Through the high and low pressure manifold liquid supply system integrated with electricity supply facilities therein according to the present disclosure, the electrically-driven fracturing units are powered, in this way, the electricity supply and distribution system in the well site can be effectively simplified, the connection distance of the cables can be shorten, and further the time spent on connection can be saved, thereby improving the well site layout efficiency.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A sacrificial layer on a substrate, an N-type doped semiconductor layer on the sacrificial layer, and a dielectric stack on the N-type doped semiconductor layer are subsequently formed. A channel structure extending vertically through the dielectric stack and the N-type doped semiconductor layer is formed. The dielectric stack is replaced with a memory stack, such that the channel structure extends vertically through the memory stack and the N-type doped semiconductor layer. The substrate and the sacrificial layer are removed to expose an end of the channel structure. Part of the channel structure abutting the N-type doped semiconductor layer is replaced with a semiconductor plug.

Abstract: Devices, systems, and methods for a vehicular safety system in autonomous vehicles are described. An example method for safely controlling a vehicle includes selecting, based on a first control command from a first vehicle control unit, an operating mode of the vehicle, and transmitting, based on the selecting, the operating mode to an autonomous driving system, wherein the first control command is generated based on input from a first plurality of sensors, and wherein the operating mode corresponds to one of (a) a default operating mode, (b) a minimal risk condition mode of a first type that configures the vehicle to pull over to a nearest pre-designated safety location, (c) a minimal risk condition mode of a second type that configures the vehicle to immediately stop in a current lane, or (d) a minimal risk condition mode of a third type that configures the vehicle to come to a gentle stop.

Abstract: Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells and a first semiconductor layer in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit of the array of memory cells including a first transistor in contact with a first side of the second semiconductor layer, and a second peripheral circuit of the array of NAND memory strings including a second transistor in contact with a second side of the second semiconductor layer opposite to the first side.

Abstract: In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes an array of memory cells. The second semiconductor structure includes a first peripheral circuit of the array of memory cells. The first peripheral circuit includes a first transistor. The first semiconductor structure or the second semiconductor structure further includes a second peripheral circuit of the array of memory cells. The second peripheral circuit includes a second transistor. The first peripheral circuit and the second peripheral circuit are stacked over one another.

Abstract: Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a stack structure includes interleaved dielectric layers and conductive layers, a channel structure extending in the stack structure, and a doped semiconductor layer arranged on the stack structure. The doped semiconductor layer covers an end of the channel structure and the stack structure, the channel structure includes a channel layer, and the channel layer includes a doped channel layer.