Patents by Inventor Kun Zhang

Kun Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220115392
    Abstract: A three-dimensional memory includes a stack structure, a dummy structure and a gate line slit. The stack structure includes gate line layers and isolation layers stacked alternatively in the vertical direction. The dummy structure includes a first dummy section and a second dummy section. The gate line slit has one end extending into a gap formed by at least one of the first dummy section or the second dummy section. At least one of the first dummy section and the second dummy section partially overlaps a projection of the gate line slit onto the horizontal plane to realize connection between the dummy structure and the gate line slit.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Inventors: Zhong Zhang, Yuhui Han, Cuicui Kong, Kun Zhang
  • Patent number: 11295765
    Abstract: A data storage device is disclosed comprising a first plurality of heads actuated over a first subset of disk surfaces by a first servo control loop comprising a first coarse actuator and a first fine actuator, and a second plurality of heads actuated over a second subset of the disk surfaces by a second servo control loop comprising a second coarse actuator and a second fine actuator. A plurality of access commands are received, wherein each access command is associated with one of the heads. While executing a first access command using the first servo control loop, a disturbance is ramped while injecting the disturbance into the second servo control loop, and the second fine actuator is calibrated based on the disturbance.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kun Zhang, Shravankumar Girish Bhat, Shrey Khanna
  • Patent number: 11294660
    Abstract: An apparatus and a method for configuring or updating a programmable logic device are provided. The apparatus includes a control module and a storage module connected to the control module. The control module includes: a JTAG interface for connecting the control module to a JTAG host, and a configuration interface compatible with a to-be-configured programmable logic device. The control module is configured to: after receiving a first control instruction including configuration information via the JTAG interface, store the configuration information into the storage module; and after receiving a configuration instruction, read the configuration information to configure the to-be-configured programmable logic device. A configuration clock used in a process that the control module configures the to-be-configured programmable logic device is generated from the to-be-configured programmable logic device, the control module or an external clock source.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 5, 2022
    Inventors: Yuanlu Xie, Kun Zhang, Haitao Sun, Jing Liu, Jinshun Bi, Ming Liu
  • Patent number: 11296801
    Abstract: A method for calibrating crystal frequency offset through a radio frequency signal includes, in Step S1, a radio frequency port of a device is connected to one end of a radio frequency cable through a copper pipe connector and the other end of the radio frequency cable is connected to a Wireless Local Area Network (WLAN) tester which is connected with a control terminal. In Step S2, a user controls the WLAN tester to test the radio frequency signal of the device through the control terminal to obtain a test result, and determines whether a deviation of the radio frequency signal is qualified. If it is qualified, the user exits the test, otherwise the user regulates the crystal circuit of the device under test, and returns to Step S2. The method may not be affected by a probe, thus the measurement may be more accurate.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 5, 2022
    Assignee: Amlogic (Shanghai) Co., Ltd.
    Inventors: Shuangqing Li, Kun Zhang, Jie Feng
  • Publication number: 20220102247
    Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a method for forming a semiconductor device includes forming a spacer structure from a first surface of the base structure into the base structure, forming a first contact portion surrounded by the spacer structure, and forming a second contact portion in contact with the first contact portion. The second contact extends from a second surface of the base structure into the base structure.
    Type: Application
    Filed: December 13, 2021
    Publication date: March 31, 2022
    Inventors: Linchun Wu, Kun Zhang, Zhong Zhang, Wenxi Zhou, Zhiliang Xia
  • Publication number: 20220093645
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a doped region of a substrate. The doped region includes dopants of a first type. The 3D memory device also includes a semiconductor layer on the doped region. The semiconductor layer includes dopants of a second type. The first type and the second type are different from each other. The 3D memory device also includes a memory stack having interleaved conductive layers and dielectric layers on the semiconductor layer. The 3D memory device further includes a channel structure extending vertically through the memory stack and the semiconductor layer into the doped region, a semiconductor plug extending vertically into the doped region, the semiconductor plug comprising dopants of the second type, and a source contact structure extending vertically through the memory stack to be in contact with the semiconductor plug.
    Type: Application
    Filed: December 7, 2021
    Publication date: March 24, 2022
    Inventors: Linchun Wu, Shan Li, Zhiliang Xia, Kun Zhang, Wenxi Zhou, Zongliang Huo
  • Patent number: 11283065
    Abstract: The present invention provides an electrode that is excellent in conductivity and improves the power density and energy density of a power storage device, a method for manufacturing the same, and a power storage device using the same. The electrode of the present invention is an electrode containing at least a graphene aggregate having a particle diameter of 0.1 ?m or more and less than 100 ?m, wherein the graphene aggregate is an aggregate of graphene basic structures each having graphene layers among which a fibrous material is located. A method for manufacturing the electrode of the present invention comprises a step of mixing the above-mentioned graphene basic structures with at least a lower alcohol having 1 or more and 5 or less carbon atoms to form a graphene aggregate in which the graphene basic structures are aggregated, and a step of forming a film using the graphene aggregate.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: March 22, 2022
    Assignee: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Jie Tang, Kun Zhang, Luchang Qin
  • Patent number: 11264717
    Abstract: A dual-band antenna, a wireless local area network (WLAN) device, and a method for manufacturing a dual-band antenna, where the dual-band antenna includes a conductive plane, a smooth curved-surface assembly joined onto the conductive plane, and a feed pin connected to the smooth curved-surface assembly. The conductive plane is configured to function as a first antenna, for receiving and sending a radio frequency signal of a first frequency band, and the smooth curved-surface assembly is configured to function as a second antenna, for receiving and sending a radio frequency signal of a second frequency band. Hence, a curved surface of a surface of the curved-surface assembly that is used as the second antenna transits smoothly. Therefore, a current is distributed relatively evenly, and radiation efficiency is relatively high.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 1, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiao Zhou, Bo Yuan, Xingfeng Jiang, Kun Zhang
  • Publication number: 20220052062
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a plurality of memory blocks in a plan view and at least one stabilization structure extending laterally to separate adjacent ones of the memory blocks in the plan view. Each of the memory blocks includes a memory stack including vertically interleaved conductive layers and first dielectric layers, and a plurality of channel structures each extending vertically through the memory stack. The stabilization structure includes a dielectric stack including vertically interleaved second dielectric layers and the first dielectric layers.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 17, 2022
    Inventor: Kun ZHANG
  • Publication number: 20220037234
    Abstract: Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.
    Type: Application
    Filed: September 14, 2020
    Publication date: February 3, 2022
    Inventors: Linchun Wu, Kun Zhang, Zhong Zhang, Wenxi Zhou, Zhiliang Xia
  • Publication number: 20220037353
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack, a first semiconductor layer, a supporting structure, a second semiconductor layer, and a plurality of channel structures. The memory stack includes vertically interleaved conductive layers and dielectric layers and has a core array region and a staircase region in a plan view. The first semiconductor layer is above and overlaps the core array region of the memory stack. The supporting structure is above and overlaps the staircase region of the memory stack. The supporting structure and the first semiconductor layer are coplanar. The second semiconductor layer is above and in contact with the first semiconductor layer and the supporting structure. Each channel structure extends vertically through the core array region of the memory stack and the first semiconductor layer into the second semiconductor layer.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 3, 2022
    Inventors: Kun Zhang, Linchun Wu, Zhong Zhang, Wenxi Zhou, Zongliang Huo
  • Publication number: 20220037352
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack including interleaved stack conductive layers and stack dielectric layers, a semiconductor layer, a plurality of channel structures each extending vertically through the memory stack into the semiconductor layer, and an insulating structure extending vertically through the memory stack and including a dielectric layer doped with at least one of hydrogen or an isotope of hydrogen.
    Type: Application
    Filed: September 14, 2020
    Publication date: February 3, 2022
    Inventors: Kun Zhang, Wenxi Zhou, Zhiliang Xia, Zongliang Huo
  • Publication number: 20220037267
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A peripheral circuit is formed on a first substrate. A first semiconductor layer is formed on a second substrate. A supporting structure and a second semiconductor layer coplanar with the supporting structure are formed on the first semiconductor layer. A memory stack is formed above the supporting structure and the second semiconductor layer. The memory stack has a staircase region overlapping the supporting structure. A channel structure extending vertically through the memory stack and the second semiconductor layer into the first semiconductor layer is formed. The first substrate and the second substrate are bonded in a face-to-face manner.
    Type: Application
    Filed: October 30, 2020
    Publication date: February 3, 2022
    Inventors: Kun Zhang, Linchun Wu, Zhong Zhang, Wenxi Zhou, Zongliang Huo
  • Patent number: 11238194
    Abstract: A structural design method of a product is provided. The method includes obtaining a preliminary design of a subsurface mesh structure by filling a body model of the product with spherical cells at preset positions of the body model and performing an finite element analysis and optimization; and optimizing, through a design method for optimizing functions, filling features of the spherical cells based on a simulation analysis so that the structure of the product satisfies a preset target.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 1, 2022
    Assignee: SOUTH UNIVERSITY OF SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Pinlian Han, Kun Zhang
  • Patent number: 11227871
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a P-type doped region of a substrate, an N-type doped semiconductor layer on the P-type doped region, a memory stack including interleaved conductive layers and dielectric layers on the N-type doped semiconductor layer, a channel structure extending vertically through the memory stack and the N-type doped semiconductor layer into the P-type doped region, an N-type doped semiconductor plug extending vertically into the P-type doped region, and a source contact structure extending vertically through the memory stack to be in contact with the N-type doped semiconductor plug.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: January 18, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Linchun Wu, Shan Li, Zhiliang Xia, Kun Zhang, Wenxi Zhou, Zongliang Huo
  • Publication number: 20220009895
    Abstract: N-nitrosaccharin of the general formula (I), wherein R is either a hydrogen (H) or a nitro group (NO2), its preparation and its use as nitrating agent.
    Type: Application
    Filed: October 24, 2019
    Publication date: January 13, 2022
    Applicant: ETH ZURICH
    Inventors: Dmitry KATAYEV, Kun ZHANG, Roxan CALVO
  • Publication number: 20220009875
    Abstract: A process for preparing a nitrated compound, including the step of reacting a compound (A) including at least one substituted or unsubstituted aromatic or heteroaromatic ring, wherein the heteroaromatic ring includes at least one heteroatom selected from the group consisting of oxygen, sulfur, phosphor, selenium and nitrogen, with a compound of formula (I) wherein Y is selected from the group consisting of hydrogen and nitro.
    Type: Application
    Filed: October 24, 2019
    Publication date: January 13, 2022
    Applicant: ETH ZURICH
    Inventors: Dmitry KATAYEV, Kun ZHANG, Roxan CALVO
  • Publication number: 20220005825
    Abstract: Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a 3D NAND memory device includes a substrate, a layer stack, memory cells, a semiconductor layer, a contact structure, and gate line slit structures. The substrate includes a doped region. The layer stack is formed over the substrate. The memory cells are formed through the layer stack over the substrate. The semiconductor layer is formed on the doped region and a side portion of a channel layer that extends through the layer stack. The contact structure electrically contacts the doped region. A dielectric material is filled in the gate line slit structures. Air gaps are formed in the gate line slit structures by the dielectric material.
    Type: Application
    Filed: August 4, 2020
    Publication date: January 6, 2022
    Inventors: Kun ZHANG, Wenxi ZHOU
  • Publication number: 20210402988
    Abstract: The disclosed technology enables automated parking of an autonomous vehicle. An example method of performing automated parking for a vehicle comprises obtaining, from a plurality of global positioning system (GPS) devices located on or in an autonomous vehicle, a first set of location information that describes locations of multiple points on the autonomous vehicle, where the first set of location information are associated with a first position of the autonomous vehicle, determining, based on the first set of location information and a location of the parking area, a trajectory information that describes a trajectory for the autonomous vehicle to be driven from the first position of the autonomous vehicle to a parking area, and causing the autonomous vehicle to be driven along the trajectory to the parking area by causing operation of one or more devices located in the autonomous vehicle based on at least the trajectory information.
    Type: Application
    Filed: June 28, 2021
    Publication date: December 30, 2021
    Inventors: Kun ZHANG, Xiaoling HAN, Zehua HUANG, Charles A. Price
  • Publication number: 20210391315
    Abstract: In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a plurality of channel structures each extending vertically through the memory stack, a conductive layer in contact with source ends of the plurality of channel structures, a first source contact electrically connected to the channel structures, and a second source contact electrically connected to the channel structures.
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventor: Kun Zhang