Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

Abstract: An optical lens assembly includes a glass lens element. The glass lens element has a refractive power, an optical surface of the glass lens element is non-planar, an anti-reflective membrane layer is formed on the optical surface, and the anti-reflective membrane layer includes a nanostructure layer and a structure connection film. The nanostructure layer has a plurality of ridge-like protrusions extending non-directionally from the optical surface, and a material of the nanostructure layer includes aluminum oxide. The structure connection film is disposed between the optical surface and the nanostructure layer, the structure connection film includes at least one silicon dioxide layer, the at least one silicon dioxide layer contacts a bottom of the nanostructure layer physically, and a thickness of the at least one silicon dioxide layer is greater than or equal to 20 nm and less than or equal to 150 nm.

Abstract: A semiconductor structure and a manufacturing method thereof are provided. The method includes the following steps. A plurality of conductive balls is placed over a circuit substrate, where each of the conductive balls is placed over a contact area of one of a plurality of contact pads that is accessibly revealed by a patterned mask layer. The conductive balls are reflowed to form a plurality of external terminals with varying heights connected to the contact pads of the circuit substrate, where a first external terminal of the external terminals formed in a first region of the circuit substrate and a second external terminal of the external terminals formed in a second region of the circuit substrate are non-coplanar.

Abstract: An imaging lens assembly includes an imaging lens element assembly, and an optical axis passes through the imaging lens assembly. The imaging lens element assembly includes a plurality of lens elements, and the lens elements includes a first lens element and a second lens element, wherein a refractive index of the first lens element is different from a refractive index of the second lens element. Each of the first lens element and the second lens element includes at least one nanostructure layer and at least one structure connection film. The nanostructure layer is irregularly arranged, the nanostructure layer includes an alumina crystal. The structure connection film is disposed between a surface of the first lens element and the nanostructure layer and between a surface of the second lens element and the nanostructure layer.

Abstract: The disclosure provides a system to simulate a simulated noise on the power zone block of a substrate. The system comprises a signal trace and a signal generating circuit. The signal trace is disposed adjacent to the power zone block. The signal generating circuit is electrically coupled to the signal trace, configured to transmit an alternating current signal over the signal trace. The alternating current signal transmitted over the signal trace is configured to induce a simulated noise on the power zone block, and a waveform of the simulated noise is determined by a frequency of the alternating current signal.

Abstract: A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Abstract: An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.

Abstract: A camera module includes an imaging lens assembly module and an image sensor. The image sensor is disposed on an image surface of the imaging lens assembly module and includes a photoelectric converting layer, a micro lens arrays layer, a light filtering layer and an anti-reflecting layer. The photoelectric converting layer is for converting a light signal to an electric signal. The micro lens arrays layer is for converging an energy of the imaging light into the photoelectric converting layer. The light filtering layer is for absorbing a light at a certain wavelength region of the imaging light. The anti-reflecting layer is disposed on a surface of at least one of the light filtering layer and the micro lens arrays layer and includes an irregular nano-crystallite structure layer and an optical connecting layer. The optical connecting layer is connected to the irregular nano-crystallite structure layer.

Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.

Abstract: A fluid handling system includes a pressure exchanger (PX) configured to receive a first fluid at a first pressure and a second fluid at a second pressure and exchange pressure between the first fluid and the second fluid. The system further includes a condenser configured to provide corresponding thermal energy from the first fluid to a corresponding environment. The system further includes a receiver to receive the first fluid output by the PX. The receiver forms a chamber to separate the first fluid into a first gas and a first liquid. The system further includes a first booster to increase pressure of a portion of the first gas to form the second fluid at the second pressure and provide the second fluid at the second pressure to the PX.

Abstract: A camera module includes an imaging lens assembly, an image sensor and an optical plate. The image sensor is disposed on an image surface of the imaging lens assembly. The optical plate is disposed between the imaging lens assembly and the image sensor, and includes a substrate and at least one anti-reflection layer. The substrate has an object-side surface and an image-side surface, the object-side surface faces towards an object side, the image-side surface faces towards an image side, and the object-side surface is parallel with the image-side surface. The at least one anti-reflection layer is disposed on the object-side surface or the image-side surface of the substrate, the anti-reflection layer includes a nanocrystal structure layer and an optical-connecting layer, wherein the nanocrystal structure layer includes a metal oxide crystal, the optical-connecting layer connects the substrate and the nanocrystal structure layer.

Abstract: A system includes a pressure exchanger (PX) configured to receive a first fluid at a first pressure, receive a second fluid at a second pressure, and exchange pressure between the first fluid and the second fluid. The first fluid is to exit the PX at a third pressure and the second fluid is to exit the PX at a fourth pressure. The system further includes a first heat exchanger configured to provide the first fluid to the PX and provide corresponding thermal energy from the first fluid to a third fluid. The system further includes a turbine configured to receive the third fluid output from the first heat exchanger. The turbine is further configured to convert corresponding thermal energy of the third fluid into kinetic energy.

Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: A plastic light-folding element includes an incident surface, an exit surface, a reflective surface and a reflective optical layer. The incident surface and the exit surface are configured to lead an imaging light enter and exit the plastic light-folding element, respectively. The reflective surface is configured to fold the imaging light. The reflective optical layer is disposed on the reflective surface, and includes an Ag layer, a bottom layer optical film and a top layer optical film. The bottom layer optical film is contacted with the Ag layer, and the bottom layer optical film is closer to the reflective surface than the Ag layer to the reflective surface. A refractive index of the top layer optical film is lower than a refractive index of the bottom layer optical film, and the top layer optical film is not contacted with the Ag layer.

Abstract: According to the present disclosure, an optical lens assembly includes at least two optical lens elements and at least one reflective element. The reflective element is made of a plastic material, the reflective element includes a reflective coating membrane, and the reflective coating membrane is disposed on a surface of the reflective element. The reflective coating membrane includes at least three coating layers of different materials, the at least three coating layers are respectively made of a first material, a second material and a third material, the first material mainly includes silver, the second material mainly includes titanium, the third material mainly includes chromium oxides, and the coating layer made of the first material and the coating layer made of the second material are disposed between the coating layer made of the third material and the reflective element.

Abstract: In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.

Abstract: A semiconductor device includes a first electronic component, a second electronic component, a third electronic component, a plurality of first interconnection structures, and a plurality of second interconnection structures. The second electronic component is between the first electronic component and the third electronic component. The first interconnection structures are between and electrically connected to the first electronic component and the second electronic component. Each of the first interconnection structures has a length along a first direction substantially parallel to a surface of the first electronic component and a width along a second direction substantially parallel to the surface and substantially perpendicular to the first direction. The length is larger than the width. The second interconnection structures are between and electrically connected to the second electronic component and the third electronic component.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: A semiconductor device includes a dielectric interposer, a first redistribution layer, a second redistribution layer and conductive structures. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first redistribution layer and the second redistribution layer. Each of the conductive structures has a tapered profile. A width of each of the conductive structures proximal to the first redistribution layer is narrower than a width of each of the conductive structure proximal to the second redistribution layer.