Patents by Inventor Kuo-In Chen

Kuo-In Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10425003
    Abstract: A power supply device is provided. The power supply device includes a power converter and a control circuit. The control circuit is coupled to a power converter. The power converter is configured to convert input power to provide output power. The control circuit is configured to receive a control signal and provide a dummy current according to the control signal and the output power, so that the sum of a current value of the dummy current and a current value of the output power is greater than or equal to a threshold value. The power converter can accordingly convert the input power in a soft switching manner.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: September 24, 2019
    Assignee: Chicony Power Techology Co., Ltd.
    Inventors: Wen-Nan Huang, Ching-Kuo Chen, Hsiao-Chih Ku, Wan-Ching Lee
  • Patent number: 10411995
    Abstract: A network system control method includes intercepting a flow modification message sent by a controller from a network protocol path between a switch and the controller so as to obtain a new flow entry; accessing a flow table of the switch so as to obtain a plurality of flow entries; inserting at least one redundant flow entry according to the new flow entry and the plurality of flow entries; performing an aggregation operation to the new flow entry, the plurality of flow entries and the at least one redundant flow entry so as to generate a set of aggregated flow entries; and updating the flow table using the set of aggregated flow entries.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: September 10, 2019
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Yu-Ching Ye, Tzu-Yu Chao, Kuo-Chen Wang
  • Publication number: 20190272528
    Abstract: A method for payment to fulfill a transaction includes steps of: by a payment certification reader of a Point of Sale (POS) terminal, reading a payment certification from an instrument cluster device of a vehicle, and transmitting the payment certification to a POS computer of the POS terminal; by the POS computer via the Internet, enabling a portable device to transmit payment information to the instrument cluster device; by the instrument cluster device, displaying the payment information; by the instrument cluster device after the transaction has been confirmed by a user operation on the vehicle, enabling the portable device to process the payment; and by the portable device, transmitting a confirmation message to the instrument cluster device.
    Type: Application
    Filed: January 25, 2019
    Publication date: September 5, 2019
    Inventors: Kuo-Chen Wu, Chen-Sheng Lin, Yi-Yang Tsai
  • Publication number: 20190250935
    Abstract: A dashboard device of a vehicle includes a storage component and a processor. The storage component stores a plurality of different language packs and a first national table listing a first number of unique language indices associated respectively with the language packs. The processor is coupled to the storage component and is programmed to, in response to receipt of a machine code and a second number related to another plurality of unique language indices from a portable electronic device, use one of the language packs to set language used on the dashboard device based on content of the machine code and a relationship between the first and second numbers.
    Type: Application
    Filed: January 25, 2019
    Publication date: August 15, 2019
    Inventors: Yi-Yang Tsai, Kuo-Chen Wu
  • Publication number: 20190248009
    Abstract: A method for programming a robot in a vision base coordinate is provided. The method includes the following steps. A robot is drawn to an operation point. The coordinates of the operation point in a photo operation are set as a new point. A teaching image is captured and a vision base coordinate system is established. A new point is added according to the newly established vision base coordinate system. When the robot is operating, the robot is controlled to capture an image from a photo operation point. A comparison between the captured image and a teaching image is made. The image being the same as the teaching image is searched according to the comparison result. Whether the vision base coordinate system maintains the same corresponding relation as in the teaching process is checked. Thus, the robot can be precisely controlled.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 15, 2019
    Inventors: Pei-Jui WANG, Chung-Hsien HUANG, Shao-Ji SHIA, Shih-Kuo CHEN, Shih-Jung HUANG
  • Publication number: 20190252261
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 10361961
    Abstract: A flow entry aggregation method of a network system includes classifying a plurality of flow entries into a plurality of partitions according to a plurality of indicators of the plurality of flow entries, wherein each flow entry utilizes ternary strings to represent at least one field of the flow entry and the plurality of indicators are utilized to indicating network requirements corresponding to the plurality of flow entries; and utilizing bit merging or subset merging to compress the flow entries in the same partition.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: July 23, 2019
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Tsung-Hsien Tsai, Kuo-Chen Wang, Wei-Feng Wu, Wei-Tso Tsai, Yu-Han Shih
  • Publication number: 20190221366
    Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 18, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Hiroshi Amaike, Kota Hattori
  • Publication number: 20190208090
    Abstract: An image processing device includes a flicker estimating circuit, a control circuit and an image processing circuit. The flicker estimating circuit estimates a flicker level of a frame according to at least one set of information corresponding to the frame to generate an estimated flicker result. The control circuit is coupled to the flicker estimating circuit, and generates at least one control signal according to the flicker level. The image processing circuit is coupled to the control circuit, and performs image processing on the frame according to the control signal.
    Type: Application
    Filed: December 17, 2018
    Publication date: July 4, 2019
    Inventors: Kuo-Chen HUANG, Yin-An JIAN, Hsing-Chih HUNG, Chung-Yi CHEN
  • Publication number: 20190204486
    Abstract: An optical film with a conductive function is provided. The optical film with the conductive function includes a liquid crystal optical compensation film and a conductive layer. The conductive layer is disposed on the liquid crystal optical compensation film.
    Type: Application
    Filed: July 9, 2018
    Publication date: July 4, 2019
    Applicant: imat corporation
    Inventors: Tsai-An Yu, Da-Ren Chiou, Shih-Ming Hung, Kuo-Chen Wu, Yi-Chien Chen, Hsiu-Yun Hsu
  • Patent number: 10333001
    Abstract: A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gin-Chen Huang, Ching-Hong Jiang, Neng-Kuo Chen, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20190172517
    Abstract: Some embodiments include an assembly having active material structures arranged in an array having rows and columns. Each of the active material structures has a first side which includes a bit contact region, and has a second side which includes a cell contact region. Each of the bit contact regions is coupled with a first redistribution pad. Each of the cell contact regions is coupled with a second redistribution pad. The first redistribution pads are coupled with bitlines, and the second redistribution pads are coupled with programmable devices. Some embodiments include methods of forming memory arrays.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 6, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kuo-Chen Wang, Martin C. Roberts, Diem Thy N. Tran, Hideki Gomi, Fredrick D. Fishburn, Srinivas Pulugurtha, Michel Koopmans, Eiji Hasunuma
  • Publication number: 20190148066
    Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.
    Type: Application
    Filed: November 16, 2017
    Publication date: May 16, 2019
    Inventors: Kuo-Chen Wang, Hiroshi Amaike, Kota Hattori
  • Patent number: 10290422
    Abstract: Some embodiments include a capacitor. The capacitor has a first electrode with a lower pillar portion, and with an upper container portion over the lower pillar portion. The lower pillar portion has an outer surface. The upper container portion has an inner surface and an outer surface. Dielectric material lines the inner and outer surfaces of the upper container portion, and lines the outer surface of the lower pillar portion. A second electrode extends along the inner and outer surfaces of the upper container portion, and along the outer surface of the lower pillar portion. The second electrode is spaced from the first electrode by the dielectric material. Some embodiments include assemblies (e.g., memory arrays) which have capacitors. Some embodiments include methods of forming capacitors.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: May 14, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Hiroshi Amaike, Kota Hattori
  • Publication number: 20190133979
    Abstract: Disclosed herein is a method for enhancing uptake of magnetic nanoparticles (MNPs) having a therapeutic agent associated therein to a target site (e.g., a tumor), thereby resulting in elevated level of therapeutic agents being accumulated in the target site. The method comprises concurrently administering a sufficient amount of a polyphenolic compound and MNPs to the target site. Also disclosed herein is a method for treating a cancer in a subject. The method comprises concurrently administering an effective amount of the polyphenolic compound and MNPs to the subject, so as to ameliorate or alleviate symptoms associated with the cancer.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 9, 2019
    Applicant: Chang Gung University
    Inventors: Yunn-Hwa MA, Yann-Lii LEU, Jender WU, Kuo-Chen WEI, Yi-Ching LU
  • Publication number: 20190130738
    Abstract: A traffic light control system includes a first traffic light apparatus and multiple second traffic light apparatuses for displaying a direction pattern indicating intended movement of an emergency vehicle about to pass through an intersection, and a controller storing direction patterns each indicating a direction to take and a specific movement manner of the emergency vehicle. In response to a direction signal corresponding to one of the direction patterns, the controller controls the first traffic light apparatus to display the one direction pattern, and controls each of the second traffic light apparatuses to display a corresponding oriented version of said one direction pattern based on a location of the second traffic light apparatus.
    Type: Application
    Filed: October 29, 2018
    Publication date: May 2, 2019
    Inventor: Kuo-Chen YU
  • Patent number: 10269649
    Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sung-Li Wang, Neng-Kuo Chen, Ding-Kang Shih, Meng-Chun Chang, Yi-An Lin, Gin-Chen Huang, Chen-Feng Hsu, Hau-Yu Lin, Chih-Hsin Ko, Sey-Ping Sun, Clement Hsingjen Wann
  • Publication number: 20190114760
    Abstract: The present invention discloses a method of evaluating image quality taken in an actual scene, the method comprising: providing a test chart placed in an actual scene, said test chart comprising a plurality of positioning patterns and a plurality of quality test patterns; capturing an image of the test chart in the actual scene; searching the plurality of positioning patterns in the image of the test chart to locate the orientation of the image of the test chart; and identifying the plurality of quality test patterns in the located image of the test chart and evaluating the image quality of the plurality of quality test patterns.
    Type: Application
    Filed: January 26, 2018
    Publication date: April 18, 2019
    Inventors: SZE-YAO NI, YUANG-TZONG LAN, KUO-CHEN WU
  • Publication number: 20190115341
    Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 18, 2019
    Inventors: Yi-Tang LIN, Clement Hsingjen WANN, Neng-Kuo CHEN
  • Patent number: 10255224
    Abstract: An intelligent PCIe slot lane assignment method applied to a motherboard including a CPU capable of providing at least 16 lanes, a switch circuit, a PCIe slot assembly consisting of a first PCIe slot, a second PCIe slot and a third PCIe slot, and a logic controller. The intelligent control of the logic controller in detection of the insertion of a PCIe expansion card in the first PCIe slot, second PCIe slot and third PCIe slot of the PCIe slot assembly enables the switch circuit to automatically assign lanes to the first PCIe slot, second PCIe slot and third PCIe slot of the PCIe slot assembly according to the detection results, increasing the convenience of expansion application and having a higher performance and expansibility.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 9, 2019
    Assignee: ADLINK TECHNOLOGY INC.
    Inventors: Hsien-Kuang Chiu, Peng-Yuan Chu, Yi-Kuo Chen, Chien-Chih Chen, Chien-Yi Hsu