Abstract: A conditional correlated multiple sampling (CCMS) single slope (SS) analog-to-digital converter (ADC) is provided. The CCMS SS ADC includes a comparator, arranged to compare an analog signal with a ramp signal and generate a comparison result; and a CCMS control circuit, arranged to determine a swing of the ramp signal according to a magnitude of the analog signal. An image sensor system using the CCMS SS ADC and a method of CCMS SS analog-to-digital conversion are also disclosed.

Abstract: A method of making a composite pixel image sensor includes forming an image sensing array; and forming a depth sensing pixel. The depth sensing pixel includes a depth sensing photodiode; a first photo storage diode; and a first transistor configured to selectively couple the depth sensing photodiode to the first photo storage diode. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the depth sensing photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node. The method includes bonding the image sensing array to the depth sensing pixel.

Abstract: A method of making a composite pixel image sensor includes forming an image sensing array; and forming a depth sensing pixel. The depth sensing pixel includes a depth sensing photodiode; a first photo storage diode; and a first transistor configured to selectively couple the depth sensing photodiode to the first photo storage diode. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the depth sensing photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node. The method includes bonding the image sensing array to the depth sensing pixel.

Abstract: One or more techniques or systems for bias control are provided herein. In some embodiments, the bias control relates to biasing of a column of one or more pixels for an image sensor. In some embodiments, an associated circuit includes a reset transistor, a source-follower transistor, a first transfer transistor, a first bias transistor, a second bias transistor, and a switch connected to the second bias transistor. In some embodiments, the first bias transistor and the second bias transistor bias a column of pixels at a first time. In some embodiments, the second bias transistor is turned off, thus removing a second bias at a second time. In this way, performance of the image sensor is improved, at least because the second bias transistor enables faster settling time when active, and a wide pixel operation range when switched off.

Abstract: A depth sensing pixel includes a photodiode; a first photo storage device; and a first transistor configured to selectively couple the photodiode to the first photo storage device. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node.

Abstract: A method for noise simulation of a CMOS image sensor comprises performing a frequency domain noise simulation for a readout circuit of the CMOS image sensor using a computer, wherein the readout circuit includes a correlated double sampling (CDS) circuit, wherein the frequency domain noise simulation includes a CDS transfer function to refer a noise introduced by the CDS circuit back to an input node of the readout circuit. The method further comprises calculating noise at the input node of the readout circuit based on the referred back noises caused by one or more components in the readout circuit and estimating noise of the CMOS imaging sensor by comparing the calculated noise at the input node of the readout circuit to an original input signal to the readout circuit of the CMOS imaging sensor.

Abstract: A CMOS sensor includes a pixel configured to output a voltage based on incident light received by the pixel. Circuitry is coupled to the pixel and is configured to determine a reset voltage of the pixel and to select a gain level based on the reset voltage of the pixel. A gain circuit is coupled to the circuitry and is configured to set a voltage level of the gain selected by the circuitry.

Abstract: One or more analog-to-digital converters and methods for analog-to-digital conversion are provided. The analog-to-digital converter comprises a ramp generator and a direct current (DC) generator respectively configured to apply a ramp voltage waveform and a DC voltage waveform to a comparator. During a pixel signal level conversion, a first portion of the ramp voltage waveform is applied to the comparator. A control circuit then makes a determination regarding an output of the comparator. If the output corresponds to a first output, or first logic state, the ramp voltage generator applies a second portion of the ramp voltage waveform to the comparator. If the output corresponds to a second output, or second logic state, the DC generator adjusts the DC voltage waveform applied to the comparator.

Abstract: A readout device comprises a readout circuit having a first switch configured to receive a pixel reset signal, a second switch configured to receive a pixel output signal, and a third switch configured to connect the first switch to the second switch. A first capacitor is connected to the first switch, a second capacitor is connected the second switch, a fourth switch is connected to the first capacitor, and a fifth switch is connected to the second capacitor. The fifth switch is connected to the fourth switch. The readout circuit also comprises a sixth switch connected to the first capacitor and a seventh switch connected to the second capacitor. The sixth switch is configured to provide a first output of the readout circuit, and the seventh is configured to provide a second output of the readout circuit.

Abstract: Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image.

Abstract: A depth sensing pixel includes a photodiode; a first photo storage device; and a first transistor configured to selectively couple the photodiode to the first photo storage device. The depth sensing pixel further includes a second photo storage diode different from the first photo storage device; and a second transistor configured to selectively couple the photodiode to the second photo storage device. The depth sensing pixel further includes a first transfer gate configured to selectively couple the first photo storage diode to a first output node. The depth sensing pixel further includes a second transfer gate configured to selectively couple the second photo storage diode to a second output node.

Abstract: A sensor system includes a pixel array, column units and a compensation circuit. The pixel array is configured to provide pixel column data. The column units are configured to generate an offset data out signal from the pixel column data. The offset data out signal includes digital offsets. The compensation circuit is configured to remove the digital offsets from the offset data out signal. The compensation circuit is also configured to generate a data out signal.

Abstract: One or more analog-to-digital converters and methods for analog-to-digital conversion are provided. The analog-to-digital converter comprises a ramp generator and a direct current (DC) generator respectively configured to apply a ramp voltage waveform and a DC voltage waveform to a comparator. During a pixel signal level conversion, a first portion of the ramp voltage waveform is applied to the comparator. A control circuit then makes a determination regarding an output of the comparator. If the output corresponds to a first output, or first logic state, the ramp voltage generator applies a second portion of the ramp voltage waveform to the comparator. If the output corresponds to a second output, or second logic state, the DC generator adjusts the DC voltage waveform applied to the comparator.

Abstract: Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image.

Abstract: A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.

Abstract: A readout device comprises a readout circuit having a first switch configured to receive a pixel reset signal, a second switch configured to receive a pixel output signal, and a third switch configured to connect the first switch to the second switch. A first capacitor is connected to the first switch, a second capacitor is connected the second switch, a fourth switch is connected to the first capacitor, and a fifth switch is connected to the second capacitor. The fifth switch is connected to the fourth switch. The readout circuit also comprises a sixth switch connected to the first capacitor and a seventh switch connected to the second capacitor. The sixth switch is configured to provide a first output of the readout circuit, and the seventh is configured to provide a second output of the readout circuit.

Abstract: A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state.

Abstract: A method for noise simulation of a CMOS image sensor comprises performing a frequency domain noise simulation for a readout circuit of the CMOS image sensor using a computer, wherein the readout circuit includes a correlated double sampling (CDS) circuit, wherein the frequency domain noise simulation includes a CDS transfer function to refer a noise introduced by the CDS circuit back to an input node of the readout circuit. The method further comprises calculating noise at the input node of the readout circuit based on the referred back noises caused by one or more components in the readout circuit and estimating noise of the CMOS imaging sensor by comparing the calculated noise at the input node of the readout circuit to an original input signal to the readout circuit of the CMOS imaging sensor.

Abstract: An apparatus comprises a readout circuit configured to be disconnected from a pixel output, and to connect a pixel reset signal received by the readout circuit to a pixel output signal received by the readout circuit. The apparatus also comprises at least one programmable gain amplifier coupled with the readout circuit. The apparatus further comprises an analog-to-digital converter coupled with the programmable gain amplifier. The readout circuit is configured to be calibrated based on a comparison of a measured output of the readout circuit to a predetermined value, the predetermined value being equal to (2n/2)?1, where n is the number of bits of the analog-to-digital converter.

Abstract: A CMOS image sensor having two ASPs can reduce increasing design difficulty as arising from a pixel array becoming larger and larger. The image sensor includes a selection circuit for transmitting outputs of CDS circuits through four divided buses to reduce parasitic loading and achieve high-speed operation. Then, the selecting circuit transmits red and blue pixels to a first ASP, and transmits green pixels to a second ASP, so as to relax the specification requirements of the ASP.