Patents by Inventor Kuo-Yu Chou
Kuo-Yu Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150116506Abstract: A method for noise simulation of a CMOS image sensor comprises performing a frequency domain noise simulation for a readout circuit of the CMOS image sensor using a computer, wherein the readout circuit includes a correlated double sampling (CDS) circuit, wherein the frequency domain noise simulation includes a CDS transfer function to refer a noise introduced by the CDS circuit back to an input node of the readout circuit. The method further comprises calculating noise at the input node of the readout circuit based on the referred back noises caused by one or more components in the readout circuit and estimating noise of the CMOS imaging sensor by comparing the calculated noise at the input node of the readout circuit to an original input signal to the readout circuit of the CMOS imaging sensor.Type: ApplicationFiled: February 11, 2014Publication date: April 30, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shang-Fu YEH, Kuo-Yu CHOU, Yi-Che CHEN, Wei Lun TAO, Honyih TU, Calvin Yi-Ping CHAO, Fu-Lung HSUEH
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Patent number: 9013610Abstract: An apparatus comprises a readout circuit configured to be disconnected from a pixel output, and to connect a pixel reset signal received by the readout circuit to a pixel output signal received by the readout circuit. The apparatus also comprises at least one programmable gain amplifier coupled with the readout circuit. The apparatus further comprises an analog-to-digital converter coupled with the programmable gain amplifier. The readout circuit is configured to be calibrated based on a comparison of a measured output of the readout circuit to a predetermined value, the predetermined value being equal to (2n/2)?1, where n is the number of bits of the analog-to-digital converter.Type: GrantFiled: August 12, 2014Date of Patent: April 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Sheng Chou, Calvin Yi-Ping Chao, Kuo-Yu Chou, Honyih Tu, Yi-Che Chen
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Publication number: 20140347535Abstract: An apparatus comprises a readout circuit configured to be disconnected from a pixel output, and to connect a pixel reset signal received by the readout circuit to a pixel output signal received by the readout circuit. The apparatus also comprises at least one programmable gain amplifier coupled with the readout circuit. The apparatus further comprises an analog-to-digital converter coupled with the programmable gain amplifier. The readout circuit is configured to be calibrated based on a comparison of a measured output of the readout circuit to a predetermined value, the predetermined value being equal to (2n/2)?1, where n is the number of bits of the analog-to-digital converter.Type: ApplicationFiled: August 12, 2014Publication date: November 27, 2014Inventors: Po-Sheng CHOU, Calvin Yi-Ping CHAO, Kuo-Yu CHOU, Honyih TU, Yi-Che CHEN
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Patent number: 8890742Abstract: A system and method is disclosed for an imaging device and/or an analog to digital converter which converts an analog input signal to a digital data signal using a comparator which compares the analog input signal to a first ramped reference signal to determine an operating point and then uses the same comparator to compare the analog input signal to a second ramped reference signal multiple times about the determined operating point.Type: GrantFiled: March 11, 2013Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Erik Tao, Calvin Yi-Ping Chao
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Patent number: 8872686Abstract: The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.Type: GrantFiled: April 8, 2013Date of Patent: October 28, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu Chou, Wei Lun Tao, Shang-Fu Yeh, Yi-Che Chen, Calvin Yi-Ping Chao
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Publication number: 20140266991Abstract: A sensor system includes a pixel array, column units and a compensation circuit. The pixel array is configured to provide pixel column data. The column units are configured to generate an offset data out signal from the pixel column data. The offset data out signal includes digital offsets. The compensation circuit is configured to remove the digital offsets from the offset data out signal. The compensation circuit is also configured to generate a data out signal.Type: ApplicationFiled: May 14, 2013Publication date: September 18, 2014Inventors: Kuo-Yu Chou, Erik Tao, Shang-Fu Yeh, Calvin Yi-Ping Chao
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Publication number: 20140266831Abstract: The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed.Type: ApplicationFiled: April 8, 2013Publication date: September 18, 2014Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.Inventors: Kuo-Yu Chou, Wei Lun Tao, Shang-Fu Yeh, Yi-Che Chen, Calvin Yi-Ping Chao
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Publication number: 20140252202Abstract: A system and method is disclosed for an imaging device and/or an analog to digital converter which converts an analog input signal to a digital data signal using a comparator which compares the analog input signal to a first ramped reference signal to determine an operating point and then uses the same comparator to compare the analog input signal to a second ramped reference signal multiple times about the determined operating point.Type: ApplicationFiled: March 11, 2013Publication date: September 11, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Yu Chou, Shang-Fu Yeh, Erik Tao, Calvin Yi-Ping Chao
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Patent number: 8830361Abstract: A method of reducing column fixed pattern noise including calibrating a readout circuit, wherein the readout circuit is electrically connected to at least one programmable gain amplifier and an analog-to-digital converter. Calibrating the readout circuit includes electrically disconnecting the readout circuit from a pixel output and electrically connecting a pixel reset input of the readout circuit to a pixel output signal input of the readout circuit. Calibrating the readout circuit further includes comparing a measured output of the readout circuit to a predetermined value and storing the comparison result in a non-transitory computer readable medium. The method further includes operating the readout circuit, the operating the readout circuit includes receiving a pixel sample signal and outputting a calibrated output based on an operating output and the stored comparison result.Type: GrantFiled: April 12, 2012Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Sheng Chou, Calvin Yi-Ping Chao, Kuo-Yu Chou, Honyih Tu, Yi-Che Chen
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Publication number: 20140217265Abstract: A CMOS sensor includes a pixel configured to output a voltage based on incident light received by the pixel. Circuitry is coupled to the pixel and is configured to determine a reset voltage of the pixel and to select a gain level based on the reset voltage of the pixel. A gain circuit is coupled to the circuitry and is configured to set a voltage level of the gain selected by the circuitry.Type: ApplicationFiled: April 11, 2014Publication date: August 7, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu CHOU, Yi-Ping CHAO, Hon-Yih TU, Po-Sheng CHOU, Yi-Che CHEN
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Publication number: 20140217263Abstract: Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image.Type: ApplicationFiled: February 5, 2013Publication date: August 7, 2014Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Kuo-Yu Chou, Calvin Yi-Ping Chao, Jhy-Jyi Sze, Honyih Tu, Fu-Lung Hsueh
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Patent number: 8767100Abstract: An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration.Type: GrantFiled: December 21, 2012Date of Patent: July 1, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Calvin Yi-Ping Chen, Honyih Tu, Kuo-Yu Chou, Po-Sheng Chou
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Patent number: 8754358Abstract: A CMOS sensor includes a pixel configured to output a voltage based on incident light received by the pixel. A first circuit is coupled to the pixel and is configured to determine a reset voltage of the pixel. A second circuit is coupled to the first circuit and is configured to select a gain level based on the reset voltage of the pixel. A gain circuit is coupled to the second circuit and is configured to set a voltage level of the gain selected by the second circuit.Type: GrantFiled: March 2, 2012Date of Patent: June 17, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu Chou, Yi-Ping Chao, Hon-Yih Tu, Po-Sheng Chou, Yi-Che Chen
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Publication number: 20140077057Abstract: A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Calvin Yi-Ping CHAO, Kuo-Yu CHOU, Fu-Lung HSUEH
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Publication number: 20140042303Abstract: A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state.Type: ApplicationFiled: October 21, 2013Publication date: February 13, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu CHOU, Calvin Yi-Ping CHAO
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Patent number: 8599292Abstract: A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state.Type: GrantFiled: August 18, 2010Date of Patent: December 3, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu Chou, Calvin Yi-Ping Chao
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Publication number: 20130271626Abstract: A method of reducing column fixed pattern noise including calibrating a readout circuit, wherein the readout circuit is electrically connected to at least one programmable gain amplifier and an analog-to-digital converter. Calibrating the readout circuit includes electrically disconnecting the readout circuit from a pixel output and electrically connecting a pixel reset input of the readout circuit to a pixel output signal input of the readout circuit. Calibrating the readout circuit further includes comparing a measured output of the readout circuit to a predetermined value and storing the comparison result in a non-transitory computer readable medium. The method further includes operating the readout circuit, the operating the readout circuit includes receiving a pixel sample signal and outputting a calibrated output based on an operating output and the stored comparison result.Type: ApplicationFiled: April 12, 2012Publication date: October 17, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Sheng CHOU, Calvin Yi-Ping CHAO, Kuo-Yu CHOU, Honyih TU, Yi-Che CHEN
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Publication number: 20130228671Abstract: A CMOS sensor includes a pixel configured to output a voltage based on incident light received by the pixel. A first circuit is coupled to the pixel and is configured to determine a reset voltage of the pixel. A second circuit is coupled to the first circuit and is configured to select a gain level based on the reset voltage of the pixel. A gain circuit is coupled to the second circuit and is configured to set a voltage level of the gain selected by the second circuit.Type: ApplicationFiled: March 2, 2012Publication date: September 5, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Yu CHOU, Yi-Ping Chao, Hon-Yih Tu, Po-Sheng Chou, Yi-Che Chen
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Patent number: 8350934Abstract: An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration.Type: GrantFiled: October 21, 2010Date of Patent: January 8, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Calvin Yi-Ping Chao, Honyih Tu, Kuo-Yu Chou, Po-Sheng Chou
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Publication number: 20120098975Abstract: An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration.Type: ApplicationFiled: October 21, 2010Publication date: April 26, 2012Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Calvin Yi-Ping Chao, Honyih Tu, Kuo-Yu Chou, Po-Sheng Chou