Abstract: A delay locked loop circuit and signal delay locking method are provided. First, the start-up circuit minimizes the delay time between an output signal and a reference signal during an initial period. Secondly, the phase correction circuit increases the delay time during an correction period. The present invention ensures that the phase difference between the output signal and the reference signal is correctly detected by the delay locked loop circuit, so that harmonic lock and phase ambiguity can be avoided.

Abstract: A delay locked loop circuit and signal delay locking method are provided. First, the start-up circuit minimizes the delay time between an output signal and a reference signal during an initial period. Secondly, the phase correction circuit increases the delay time during an correction period. The present invention ensures that the phase difference between the output signal and the reference signal is correctly detected by the delay locked loop circuit, so that harmonic lock and phase ambiguity can be avoided.

Abstract: A current steering digital-to-analog converter (DAC) is provided. At least two lower-resolution DACs are used for converting a high-resolution digital signal. One of the two lower-resolution DACs is used for converting the most significant bits (MSB) of the high-resolution digital signal. The other of the two lower-resolution DACs is used for converting the least significant bits (LSB) of the high-resolution digital signal. By such arrangement, a device mismatch problem is avoided and the chance of variation occurrence during manufacturing process is reduced. The arrangement also simplifies the layout in the significantly scaled-down chip area.

Abstract: A digital-to-analog converter (DAC) is disclosed, which provides different bias voltages to the most significant bits (MSBs) and the least significant bits (LSBs) of the digital signal. These two bias voltages can be adjusted according to the match among the current source cells, and maintain a particular proportional relationship. The DAC further includes a bias converter for receiving the first bias voltage, and adjusting the second bias voltage according to the match among the current source cells.

Abstract: A digital-to-analog converter (DAC) is disclosed, which provides different bias voltages to the most significant bits (MSBs) and the least significant bits (LSBs) of the digital signal. These two bias voltages can be adjusted according to the match among the current source cells, and maintain a particular proportional relationship. The DAC further includes a bias converter for receiving the first bias voltage, and adjusting the second bias voltage according to the match among the current source cells.

Abstract: An image sensing device includes a pixel sensing data processing unit, for receiving a pixel line sensing data to output first and second outputs. A controller receives the first output from the pixel sensing data processing unit, checks whether the pixel line sensing data include at least one defective pixel. If it has defective pixel, a correction rule is applied to compare the status data with a previously defective pixel. The correction rule includes comparing a state data of the previous defect pixels. If the defective pixel belongs to a regular pattern, the defective pixel is not corrected. A correction unit receives the second output and receives the correction status from the controller, and to correct the pixel and exports a display data. A recording unit records the status data of the defective pixel detected by the controller for comparing the status data of the next pixel line sensing data.

Abstract: An automatic clock generation system is used for automatically outputting a sampling signal and a holding signal to an analog front end circuit and for sampling the analog signal. The clock generation system comprises a clock generator generating a plurality of clock signals and a comparing module. According to the plurality of clock signals, the comparing module compares the analog signal with a first reference signal and outputs a first comparison signal. The comparing module further compares the digital signal outputted by the analog front end circuit with a second reference signal and outputs a second comparison signal. The clock generator selectively outputs a first clock signal, corresponding to the first comparison signal, of the plurality of clock signals as the sampling signal when the first comparison signal received by the clock generator is at a high state.

Abstract: The invention provides a transient voltage detecting circuit for detecting changes of voltage in an electronic system which has a first power supply (VDD), a second power supply (VDD), a third power supply (VDD), a fourth power supply (VDD), a first ground (GND), and a second ground (GND). The voltage of the first VDD is substantially equal to that of the second VDD. The voltage of the third VDD is substantially equal to that of the fourth VDD. The voltage of the first GND is substantially equal to that of the second GND. The circuit according to the invention can detect a positive or negative transient voltage once that occurs at the first VDD, the second VDD, the third VDD, or the fourth VDD.

Abstract: The invention provides a circuit for detecting a transient voltage for an electronic system having a power supply port and a ground port. The circuit includes a capacitor, a rectifying device, a pre-set resistance device and a detecting device. According to one preferred embodiment of the invention, the detecting device has an input coupled to a second terminal of the capacitor. Once the transient voltage occurs at the power supply port, and when the voltage at the second terminal of the capacitor is higher than a threshold voltage, the detecting device outputs an output voltage for representing occurrence of the transient voltage.

Abstract: The invention provides a transient voltage detecting circuit for detecting a transient voltage occurring at a power supply or a ground of an electronic system. The circuit according to the invention includes a plurality of detecting units of which the outputs are initially latched by at least one voltage source. The circuit also includes a detecting device outputting a first logic according to the initial outputs of all of the detecting units. When the transient voltage occurs, it is ensured that the logic of the output of one of the detecting units is changed by the transient voltage or the decayed transient voltage, such that the decision device renewably outputs a second logic to trigger a resetting device of the electronic system in accordance with the outputs of all of the detecting units.

Abstract: An analog front end circuit comprises a variable gain amplifier circuit (VGA circuit), a first sample switch, a second sample switch, a hold switch and an analog to digital converter device. The VGA circuit comprises a first input end, a second input end, and at least one output end. The first input end is used for receiving first voltage level signals. The second input end is used for receiving first reference signals. The output end is used for outputting at least one amplified signal. While the first sample switch is at a first conductive state, the first input end receives the first voltage level signal. While the second sample switch is at the first conductive state, the second input end receives the first reference signal. Finally, while the hold switch is at a second conductive state, the output end outputs the amplified signal.

Abstract: The present invention is a correction system applying in an analog front end(AFE). The correction system comprises a correction module, a first digital to analog converter(DAC1) and a second digital to analog converter(DAC2). The correction is used to generate a gain error correction and black pixel signal error correction when the black pixel signal is inputted into the AFE. The correction module corrects the digital output signals generated by the AFE according to the gain error correction. The correction module input the black pixel signal error correction to the DAC1 to generate a first analog correction signal to correct the signal inputted into the AFE. The present invention effectively corrects the signal error generated by the AFE to make the AFE output the corrected digital output signal.

Abstract: This present invention is directed to a stage circuit for a pipelined analog-to-digital converter. The stage circuit includes an amplifier, a comparator, a first compensator and a second compensator, and three modes are developed for the stage circuit in signal processing: a sampling mode, a first amplifying mode and a second amplifying mode. In the sampling mode, the amplifier is inputted with an analog input signal; the comparator compares the analog input signal with a reference signal, and then generates a first digital output code. In the first amplifying mode, the first compensator selectively adds a first compensation value to the analog input signal according to the first digital output code, and then generates a first input signal; the amplifier amplifies the first input signal and then generates a first output signal; the comparator compares the first output signal with the reference signal and then generates a second digital output signal.

Abstract: The present invention is a pipelined analog-to-digital converter (Pipelined ADC) for converting a first analog signal to a digital data. The converter comprises at least one first stage circuit, at least one second stage circuit, a third stage circuit, and a code adder. Each of the first stage circuits has a first converting rate for converting a first analog signal to at least one digital code and generating a second analog signal. The second stage circuits are serially connected after the first stage circuit. Each of the second stage circuits has a second converting rate which is higher than the first converting rate for converting the second analog signal to at least two digital codes and generating a third analog signal. The third stage circuit serially connected after the second stage circuits is used for converting the third analog signal to at least one digital code. The code adder is used for combining the digital codes to generate the digital data.

Abstract: The present invention provides a correction system and method for a Successive Approximation A/D Converter (SA-ADC) of the prior art. The operation method of the correction system is described in the following: (1) Using the SA-ADC of the prior art to convert an analog signal to a digital data. The digital data is a series of logic numbers. (2) Detecting the last number of the digital data is logic number [0] or logic number [1]. (3-1) When the last number is logic number [1], proceeding the digital data and logic number [1] with an addition operation to generate a first detection digital data. Converting the first detection digital data to a first detection signal for comparing with the analog signal. If the analog signal is higher than the first detection signal, then replacing the digital data by the first detection digital data. If the analog signal is lower than the first detection signal, then outputting the digital data without correcting.

Abstract: This present invention is directed to a stage circuit for a pipelined analog-to-digital converter. The stage circuit includes an amplifier, a comparator, a first compensator and a second compensator, and three modes are developed for the stage circuit in signal processing: a sampling mode, a first amplifying mode and a second amplifying mode. In the sampling mode, the amplifier is inputted with an analog input signal; the comparator compares the analog input signal with a reference signal, and then generates a first digital output code. In the first amplifying mode, the first compensator selectively adds a first compensation value to the analog input signal according to the first digital output code, and then generates a first input signal; the amplifier amplifies the first input signal and then generates a first output signal; the comparator compares the first output signal with the reference signal and then generates a second digital output signal.

Abstract: A semiconductor substrate has a V-shape structure positioned in the semiconductor substrate. A first ion implantation process is then performed to form a first doping region around the V-shape structure in the semiconductor substrate. Following this, a first dielectric layer is formed on surfaces of the semiconductor substrate and the first doping region. A floating gate is formed on the first dielectric layer over the first doping region and a second dielectric layer is formed on the floating gate, respectively. A controlling gate is then formed on the second dielectric layer. Finally, a second ion implantation process is performed utilizing the controlling gate as a mask to form a second doping region in the semiconductor substrate.

Abstract: A method for forming a wiring bond pad utilized in wire bonding operations on an integrated circuit device is disclosed herein, including a wiring bond apparatus thereof. A wiring bond pad may be configured to comprise a single metal layer. At least one integrated circuit device may be positioned below the wiring bond pad to thereby conserve integrated circuit space and improve wiring bond pad efficiency as a result of configuring the wiring bond pad as a single metal layer wiring bond pad. The wiring bond pad may thus be configured as a single metal layer wiring bond pad. The single metal layer is generally located above a plurality of intermetal dielectric layers. The integrated circuit device may also be located below the plurality of intermetal dielectric layers.

Abstract: A vertical structure and a method of forming a vertical structure are disclosed. A partially processed semiconductor wafer is provided having all devise levels completed, including a topmost interlevel dielectric layer through which metallic vias are formed for electrical connection. A first metal level is formed. An IMD level is then formed by forming a blanket dielectric layer over the first metal level, patterning and etching the dielectric layer to form arrays of trenches passing through the dielectric layer, filling the trenches with a conducting material, and performing CMP. A number of metal level, IMD level pairs are formed, where the number could be zero. Bonding metal patterns are deposited, wires are bonded onto the bonding metal patterns and a passivation layer is formed.

Abstract: Within both a microelectronic fabrication and a method for fabricating the microelectronic fabrication, there is employed at least one fuse layer electrically connected with a series of patterned conductor layers separated by a series of dielectric layers, where the at least one fuse layer is formed at a level no lower than a highest of the series of patterned conductor layers within the microelectronic fabrication. When formed within the context of the foregoing constraint, there is provided enhanced access for actuation of the at least one fuse layer within the microelectronic fabrication.