Abstract: The present invention provides a method of erasing data in a flash memory. The flash memory has a number of memory units for storing data. The method has involves repeatedly performing an erasing process along a first erasing route to erase data stored in each memory unit, and if after a predetermined number of erasing times, data in each memory unit is not completely erased, a second erasing route to perform the erasing process is utilized.

Abstract: A semiconductor wafer includes a plurality of sensors. Each of the sensors has a field oxide transistor, and a detecting circuit electrically connected to the field oxide transistor for detecting if the field oxide transistor is switched on or off and generating corresponding detecting signals. The field oxide of a different field oxide transistor has a different thickness. Each field oxide transistor is coupled to a corresponding detecting circuit for detecting radiation impinging on the semiconductor wafer.

Abstract: A flash memory circuit has a flash memory array and a processor. The flash memory array has a plurality of erasable flash memory cells. Each of the flash memory cells is electrically connected to a corresponding bitline. If any over-erased flash memory cell exists in the flash memory array, a processor controls the flash memory circuit to apply a correction voltage to the bitline connected to the over-erased flash memory cell so as to correct the over-erased flash memory cell. The correction voltage is continuously applied until a current along the corresponding bitline drops below a predetermined value.

Abstract: A combinational inductor, which can be constructed on a surface of a semiconductor substrate or an isolator, is provided. The combinational inductor includes several spiral inductors which are connected together in series. The spiral inductors can be constructed on the same layer to produce a combinational inductor structure, because of the same metalization process used. In another aspect, connecting methods between neighboring spiral conductors include forward cascade and reverse cascade. A spiral conductor has at least one neighboring spiral conductor which is connected with it in reverse cascade. The inductance per unit square measurement of the inductor in series can be significantly increased through the connections between neighboring spiral conductors either in forward cascade or reverse cascade.

Abstract: A method to form a shallow trench isolation (STI) structure includes forming a trench on a semiconductor substrate. Then a channel stop is formed under the trench. A pad oxide layer and a silicon nitride layer are sequentially formed over the substrate. A side-wall spacer is formed over the silicon nitride layer on each side of the trench. An oxidation process is performed to oxidize the side-wall spacer. Another side-wall spacer and oxidation are repeatedly performed until the trench is filled with oxide. An oxide layer is formed over the substrate. Then an active ion etching process is performed to remove the layers above the substrate other than the trench region. The STI structure then is formed.

Abstract: A method for fabricating a static random access memory polyload resistor comprising the steps of first providing a semiconductor substrate having a transistor formed thereon, wherein the transistor includes a gate, a source region and a gate region. Thereafter, a dielectric layer is formed over the substrate, and then photolithographic and etching processes are used to remove a portion of the dielectric layer forming a plurality of vias. Next, a polysilicon layer is formed over the substrate, and then photolithographic and etching processes are again used to pattern the polysilicon layer. Then, ions are doped to form a doped polysilicon layer. In the subsequent step, an anti-oxidation layer is formed over the substrate. Then, photolithographic and etching processes are again used to remove a portion of the polysilicon layer and the anti-oxidation layer forming interconnect regions and load resistor regions. Finally, a thermal oxidation is carried out followed by the removal of the anti-oxidation layer.

Abstract: A process is disclosed for the fabrication of a MOS device with a T-shaped gate electrode, in which a selective CVD technique has been utilized to simplify the T-shaped gate process. After the formation of the gate oxide layer, no reactive ion etching step is applied, and that avoids the plasma charging damage to the gate oxide. The lightly-doped-drain structure and heavily-doped drain and source areas are formed in a self-aligned manner during the T-shaped gate process. The present invention provides a high yield rate and cost-saving in the T-shaped gate process for MOS devices.

Abstract: A modified gate structure for a non-volatile memory device is formed over a substrate. The modified gate structure from bottom to top comprises a first dielectric layer, a first conductive layer, a second dielectric layer formed on said first conductive layer, a third dielectric layer, a refractory metal layer, and a second conductive layer. The third dielectric layer is made of tantalum oxide or BST, and the refractory metal layer can be made of tungsten, platinum, titanium, molybdenum, and tantalum.

Abstract: A method of fabricating a stacked type capacitor. A semiconductor substrate having a transistor, a field oxide layer, and a conductive layer formed on top of the field oxide layer is provided. The transistor comprises a gate and a source/drain region. A first dielectric layer is formed over the substrate. An oxide layer is formed over the first dielectric layer. A second dielectric layer is formed on the oxide layer. An etching step is performed to the second dielectric layer to form an opening therein. A first poly-silicon layer is formed on the second dielectric layer and the opening. The first poly-silicon layer is etched back to remove a part of the first poly-silicon layer. A first spacer is formed on a wall of the opening. The oxide layer is etched for a first height by using the first spacer and the second dielectric layer as a first mask. A second poly-silicon layer is formed on the second dielectric layer and the opening.