Abstract: A method of operating an electronic device that is configured to support manufacturing a semiconductor device includes (i) selecting a height of a stage of the electronic device that is configured to hold the semiconductor device, (ii) generating white light by using a light source of the electronic device, (iii) generating light of a selected wavelength by filtering the white light using a monochromater of the electronic device, (iv) emitting the light of the selected wavelength to the semiconductor device using a beam splitter of the electronic device, and (v) capturing reflection light reflected from the semiconductor device using a camera of the electronic device.

Abstract: Disclosed are three-dimensional (3D) semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a substrate, a stack structure including interlayer dielectric layers and gate electrodes that are alternately stacked on the substrate, and vertical channel structures that fill vertical channel holes that penetrate the stack structure. Each of the vertical channel structures includes a vertical semiconductor pattern and a data storage pattern that surrounds the vertical semiconductor pattern. The data storage pattern includes a first gate dielectric layer, a ferroelectric pattern, a first channel dielectric layer, and a second channel dielectric layer that are sequentially provided on an inner sidewall of each of the vertical channel holes.

Abstract: A system for nondestructive measurement of a sample, the system includes a stage configured to support the sample thereon; a light source unit configured to output a pump beam having a first inspection wavelength and a probe beam having a second inspection wavelength; a beam delayer configured to delay a path of one of the pump beam and the probe beam; an optical system configured to provide the pump beam and the probe beam to the sample; a detector configured to detect the probe beam reflected from the sample; and a processor configured to: determine at least one of the first inspection wavelength and the second inspection wavelength so that a change in a reflectance at which the probe beam is reflected from the sample is maximized; and determine characteristics of the sample based on the probe beam reflected from the sample.

Abstract: A gate driver can include a level shifter configured to output first-mode gate clocks in a normal scan rate mode and output second-mode gate clocks in a high scan rate mode, and a gate shift register configured to output normal scan rate scan signals synchronized with the first-mode gate clocks in the normal scan rate mode and output high scan rate scan signals synchronized with the second-mode gate clocks in the high scan rate mode. Adjacent gate clocks of the first-mode gate clocks have a phase difference equal to 1 horizontal period, and adjacent gate clock pairs of the second-mode gate clocks have a phase difference equal to 1 horizontal period and two gate clocks configuring the same gate clock pair are synchronized with each other. The first-mode gate clocks are implemented as a 16-phase clock and the second-mode gate clocks are implemented as a 16-phase clock.

Abstract: A semiconductor memory device includes a cell substrate; a mold structure which includes word lines, a voltage bias film, and a string selection line stacked sequentially on the cell substrate; a channel hole which penetrates the mold structure; and a channel structure inside the channel hole, wherein the channel hole includes a first portion penetrating the word line, a second portion penetrating the voltage bias film, and a third portion penetrating the string selection line, a width of a lowermost part of the second portion is greater than a width of an uppermost part of the first portion, and a width of an uppermost part of the second portion is greater than a width of a lowermost part of the third portion.

Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

Abstract: A liquid leak detection apparatus includes: a frame having a container structure and including a liquid collection surface at an upper part of the frame; and a liquid leak sensor on the liquid collection surface, wherein the liquid collection surface comprises a liquid collection portion that is disposed on one side of the liquid collection surface, wherein the liquid collection portion is lower in height by a predetermined value than a region where a height of an up-down direction is the greatest in the liquid collection surface, and wherein the liquid leak sensor is on the liquid collection portion.

Abstract: A semiconductor device includes: a substrate; a gate stacking structure that includes interlayer insulating layers and gate electrodes that are alternately stacked on the substrate; a channel structure that penetrates the gate stacking structure and extends in a first direction, and includes a channel layer connected to the substrate and a ferroelectric layer that surrounds the channel layer; a charge inflow pattern disposed on a lateral side of the ferroelectric layer and spaced apart in the first direction; and an insulation pattern disposed between the charge inflow pattern and the gate electrodes and that surrounds an exterior side, a lower side, and an upper side of the charge inflow pattern.

Abstract: A semiconductor device includes: a sampling control circuit configured to select a coarse section from a plurality of coarse sections according to a first pattern signal during a sampling period, select a fine section from a plurality of fine sections according to a second pattern signal during the selected coarse section, and generate first to third sampling control signals having activated sections defined by the selected coarse section and the selected fine section; and a sampling circuit configured to sample an input address according to the first to third sampling control signals, respectively, to generate first to third sampling addresses, and schedule the first to third sampling addresses according to a sampling signal defining the sampling period to output an output address.

Abstract: A semiconductor device includes: a substrate, a gate stacking structure that includes a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on the substrate, a channel layer that extends in a first direction and into the gate stacking structure, where the channel layer is electrically connected to the substrate, a channel insulating layer that at least partially surrounds the channel layer, and a plurality of dielectric layers that are between the channel insulating layer and the plurality of gate electrodes, extend along a circumference of the channel layer, and are spaced apart from each other in the first direction, where each of the plurality of dielectric layers includes: a ferroelectric pattern that at least partially surrounds the channel insulating layer, and an anti-ferroelectric pattern that at least partially surrounds the ferroelectric pattern.

Abstract: An example includes: a package substrate having a die pad with a device side surface and a thermal pad on an opposite side surface; a thermal dissipation structure mounted to the die pad, the thermal dissipation structure including a thermally conductive insulator core and thermal conductors on a device side surface and on a substrate mount surface opposite the device side surface; at least one semiconductor device die mounted to the device side surface of the thermal dissipation structure; electrical connections formed between leads on the package substrate and bond pads on the at least one semiconductor device die; and mold compound covering the electrical connections, the at least one semiconductor device, and portions of the package substrate, portions of the leads of the package substrate forming terminals, and the thermal pad exposed from the mold compound and forming a thermal pad for a semiconductor device package.

Abstract: A semiconductor package includes a first redistribution layer structure, a first set of semiconductor dies on the first redistribution layer structure, a plurality of connection members on the first redistribution layer structure and around the first set of semiconductor dies, a molding material on the first redistribution layer structure, the molding material covering the first set of semiconductor dies and at least partially surrounding the plurality of connection members, a second redistribution layer structure on the molding material, a second set of semiconductor dies on the second redistribution layer structure, and a dummy structure on the second redistribution layer structure and between a first semiconductor die of the second set of semiconductor dies and a second semiconductor die of the second set of semiconductor dies.

Abstract: A semiconductor package includes a redistribution structure, a semiconductor die on the redistribution structure, one or more memory stacking structures disposed on the redistribution structure, wherein the one or more memory stacking structures and the semiconductor die are arranged side by side on the redistribution structure, an optical engine disposed on the redistribution structure, wherein the optical engine and the semiconductor die are arranged side by side on the redistribution structure, and a heat dissipation structure on the semiconductor die, the one or more memory stacking structures, and the optical engine, wherein levels of upper surfaces of the semiconductor die, the one or more memory stacking structures, and the optical engine are the same.

Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, a first mold layer at least partially covering the first redistribution substrate and the first semiconductor chip, a plurality of first conductive pillars at least partially penetrating the first mold layer and contacting the first redistribution substrate, a second redistribution substrate on the first mold layer, a second semiconductor chip on the second redistribution substrate, a second mold layer at least partially covering the second redistribution substrate and the second semiconductor chip, a plurality of second conductive pillars at least partially penetrating the second mold layer and contacting the second redistribution substrate, and a third redistribution substrate on the second mold layer. The first semiconductor chip includes a first through via. The second semiconductor chip includes a backside power delivery network layer.

Abstract: A semiconductor package includes a redistribution layer structure, a first sub-package positioned on the redistribution layer structure, a second sub-package positioned on the first sub-package, and a first encapsulant positioned on the first sub-package and encapsulating the second sub-package. The first sub-package includes a first semiconductor chip including a first chip through via and a dielectric through via electrically connected to the redistribution layer structure. The second sub-package includes a second semiconductor chip including a plurality of second chip through vias, each second chip through via electrically connected to one of the first chip through via and the dielectric through via, a third semiconductor chip positioned on the second semiconductor chip, and a fourth semiconductor chip positioned on the third semiconductor chip. Each of the second to fourth semiconductor chips is exposed at a side surface of the second sub-package and covered with the first encapsulant.

Abstract: An electronic device includes a first semiconductor die attached to a first conductive die attach pad and having a first electronic component, a second semiconductor die attached to a second conductive die attach pad and having a second electronic component, a first package structure that encloses the first semiconductor die and a portion of the first die attach pad, a second package structure that encloses the second semiconductor die and a portion of the second die attach pad, and a conductive metal structure that is electrically connected to the first and second electronic components and extends between the first and second package structures, the conductive metal structure exposed outside the first and second package structures.

Abstract: A three-dimensional semiconductor memory device may include a stack including gate electrodes and insulating layers, which are alternatingly stacked on a substrate, vertical channel structures penetrating the stack, and data storage patterns between the stack and the vertical channel structures. The data storage patterns may be spaced apart from each other in a direction perpendicular to a top surface of the substrate, and each of the data storage patterns may include a ferroelectric pattern, an anti-ferroelectric pattern, and a first insulating pattern.

Abstract: An electronic device includes a package structure, conductive leads, first and second semiconductor dies, and a metal clip, The package structure has opposite longitudinal ends, opposite lateral sides, a middle portion midway between the longitudinal ends, a first portion that extends between the middle portion and one longitudinal end, and a second portion that extends between the middle portion and the other longitudinal end. The metal clip extends in the package structure from the first portion to the second portion through the middle portion and electrically couples the first electronic component of the first semiconductor die to the second electronic component of the second semiconductor die.

Abstract: A semiconductor package includes a first semiconductor chip having a front side and a back side that is opposite to the front side, the first semiconductor chip includes a front side wiring structure disposed on the front side, a back side wiring structure disposed on the back side, and a first through via electrically connected to the front side wiring structure and the back side wiring structure, a second semiconductor chip disposed on the back side of the first semiconductor chip and including a second through via, and a third semiconductor chip disposed on the front side of the first semiconductor chip, wherein the first semiconductor chip receives power through the second through via, and wherein a thickness of the second semiconductor chip is greater than a thickness of the first semiconductor chip.

Abstract: A semiconductor device includes first to third semiconductor chips consecutively stacked. The first semiconductor chip comprises a first semiconductor substrate. A circuit layer is on a top surface of the first semiconductor substrate. First pads are on a top surface of the circuit layer. The first pads are electrically connected to the circuit layer. The second semiconductor chip comprises a second semiconductor substrate. Passive devices are in the second semiconductor substrate. Second pads are on a bottom surface of the second semiconductor substrate. The second pads are electrically connected to the passive devices. Third pads are on a top surface of the second semiconductor substrate. The third semiconductor chip comprises fourth pads on a bottom surface of the third semiconductor chip. The first pads and the second pads are directly connected to each other. The third pads and the fourth pads are directly connected to each other.