Abstract: A method of manufacturing a stacked structure includes forming a first metal buffer layer including crystal grains on a base substrate, forming a second metal buffer material layer on the first metal buffer layer, and crystallizing the second metal buffer material layer to form a second metal buffer layer, wherein the second metal buffer material layer includes crystal grains, and a density of the crystal grains of the second metal buffer material layer is lower than a density of the crystal grains of the first metal buffer layer.

Abstract: Disclosed herein are methods of generating induced pluripotent stem cells. The method involves providing a quantity of somatic or non-embryonic cells, contacting the contacting the somatic or non-embryonic cells with a quantity of one or more programming factors and one or more RNA molecules, and culturing the somatic or non-embryonic cells for a period of time sufficient to generate at least one induced pluripotent stem cell. Various reprogramming factors and RNA molecules for use in the methods are disclosed herein. Also disclosed are cell lines and pharmaceutical compositions generated by use of the methods.

Abstract: An electronic device includes an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.

Abstract: The present invention relates to a saccharide syrup composition comprising an organic acid or its salt and an oligosaccharide, and more specifically, the saccharide syrup composition comprises allulose.

Abstract: The present invention relates to an allulose syrup and method of preparing the same, and more specifically, an allulose syrup with proper viscosity ranges, including viscosity-regulating agent and a dispersant and method of preparing the same.

Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

Abstract: A power module includes an interconnect of an integrated circuit (IC) package having a heat slug. The power module also includes a direct bonded copper (DBC) substrate. The DBC substrate has a first surface formed of pattern copper, the patterned copper has a pad and a second surface that opposes the first surface, the second surface has a sheet of copper. The second surface of the DBC substrate is thermally coupled to the heat slug. The power module further includes a die mounted on the pad of the first surface of the DBC substrate. The die has a power transistor. The die and the heat slug are thermally coupled and electrically isolated.

Abstract: The present application provides compounds and methods, e.g., for activating Nurr 1 and for treating diseases and conditions in which Nurr 1 is implicated.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

Abstract: A described example includes: a heat slug having a board side surface and an opposite top side surface; a package substrate mounted to the heat slug, the package substrate including overhanging leads extending over the board side surface of the heat slug, the package substrate having downset portions including a downset rail that runs along one side of a die mount area; at least one semiconductor device having a backside surface mounted to the board side surface of the heat slug; electrical connections coupling bond pads of the semiconductor device to the overhanging leads of the package substrate and to the downset rail; and mold compound covering the at least one semiconductor device, the electrical connections, a portion of the leads and the board side surface of the heat slug, the top side surface at least partially exposed from the mold compound.

Abstract: An IC package includes an interconnect having a first platform and a second platform that are spaced apart. The IC package includes a die superposing a portion of the first platform of the interconnect. The die has a field effect transistor (FET), and a matrix of pads for the FET situated on a surface of the die. The matrix of pads having a row of source pads and a row of drain pads. A drain wire bond extends from a first drain pad to a second drain pad of the row of drain pads and to the first platform of the interconnect. A source wire bond extends from a first source pad to a second source pad of the row of source pads, back over the first source pad and is coupled to a connection region of the first platform.

Abstract: Disclosed is a semiconductor package comprising a substrate that includes a plurality of substrate pads on a top surface of the substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip, and a plurality of first bonding wires on a top surface of the first semiconductor chip and coupled to the substrate pads. The first semiconductor chip includes a first lower signal pad, a second lower signal pad laterally spaced apart from the first lower signal pad, and a lower signal redistribution pattern electrically connected to the first lower signal pad and the second lower signal pad. One of the first bonding wires is coupled to the first lower signal pad. Any of the first bonding wires is not on a top surface of the second lower signal pad.

Abstract: An electronic device for use in power related applications includes a multi-layered substrate comprised of a first metal layer, a second metal layer, and an intermediate layer disposed between the first metal layer, and the second metal layer. The first metal layer is partitioned into sections, where each of the sections has a first surface and electrical circuits patterned onto the first surface. A lead frame is attached to outer portions of the first metal layer and a die is attached to the first surface of each of the sections of the first metal layer.

Abstract: Provided herein are methods and compositions for treating a Nurr1-mediated and/or PPAR?-mediated condition. Also provided herein are methods and compositions for increasing Nurr1 or PPAR? activity and/or levels in a cell.

Abstract: A optical measurement apparatus includes: an optical system which generates a pupil image of a measurement target, using light; a polarization generator which generates a polarized light from the light; a self-interference generator which generates a plurality of beams divided from the pupil image, using the polarized light, and causes the plurality of beams to interfere with each other to generate a self-interference image; and an image analysis unit configured to extract phase data from the self-interference image, and to move the measurement target to a focus position on the basis of the phase data.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

Abstract: The present disclosure provides a saccharide syrup composition, especially a saccharide syrup composition satisfying specific physical properties and a manufacturing method thereof.

Abstract: Various embodiments of the present invention relate to a secondary battery. The technical problem to be solved is to provide the secondary battery which can improve the insulation strength of first and second multi-tabs, by forming the first and second multi-tabs of first and second electrode assemblies symmetrically with respect to each other, and also can improve the insulation strength of the first and second multi-tabs by forming an insulating layer on the first and second multi-tabs of the first and second electrode assemblies.

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having an exposed region of a first silicon-containing material and an exposed region of a second silicon-containing material. The second silicon-containing material may be exposed within a recessed feature defined by the substrate. The methods may include flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the semiconductor processing chamber to generate plasma effluents of the fluorine-containing precursor and the silicon-containing precursor. The methods may include contacting the substrate with the plasma effluents. The methods may include removing at least a portion of the second silicon-containing material.

Abstract: Disclosed is an antenna control method and apparatus. The antenna control method includes determining an azimuth angle of an antenna based on ephemeris information of a satellite, determining an elevation angle and a cross level of the antenna based on the azimuth angle and controlling the antenna based on the azimuth angle, the elevation angle, and the cross level.