Abstract: A semiconductor memory device includes gate electrodes arranged on a substrate to be spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, an upper insulation layer arranged on an uppermost gate electrode, channel structures penetrating through the upper insulation layer, and the gate electrodes in the first direction, and string selection line cut insulation layers horizontally separating the upper insulation layer and the uppermost gate electrode. Each of the string selection line cut insulation layers includes a protrusion protruding toward the uppermost gate electrode and positioning on the same level as the first gate electrode.

Abstract: Disclosed are an apparatus for and a method of performing an inspection and metrology process. The apparatus may include a stage configured to load a substrate thereon, a sensor on the stage, an object lens between the sensor and the stage, a light source generating an illumination light to be transmitted to the substrate through the object lens, a first band filtering part between the light source and the object lens to control a wavelength of the illumination light within a first bandwidth, and a second band filtering part between the light source and the object lens to control a wavelength of the illumination light within a second bandwidth, which is smaller than the first bandwidth.

Abstract: Provided herein are methods and compositions for treating a Nurr1-mediated and/or PPAR-mediated condition. Also provided herein are methods and compositions for increasing Nurr1 or PPAR activity and/or levels in a cell.

Abstract: A three-dimensional semiconductor memory device includes a plurality of first insulating layers vertically stacked on a peripheral logic structure, second insulating layers stacked alternately with the first insulating layers, conductive layers stacked alternately with the first insulating layers and disposed on sidewalls of the second insulating layers, through-interconnections penetrating the first insulating layers and the second insulating layers so as to be connected to the peripheral logic structure, and a first conductive line electrically connected to a plurality of first conductive layers of the conductive layers.

Abstract: A three-dimensional semiconductor memory device includes: a base substrate; a gate stack structure disposed on the base substrate, and including gate electrodes stacked in a direction substantially perpendicular to a top surface of the base substrate; a penetration region penetrating through the gate stack structure and surrounded by the gate stack structure; and vertical channel structures passing through the gate stack structure. The lowermost gate electrodes among the gate electrodes are spaced apart from each other, and a portion of at least one of the lowermost gate electrodes has a shape bent toward the penetration region.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate and a stacked structure in which a plurality of insulating layers and a plurality of electrode layers are alternately stacked on the substrate. The semiconductor device includes a plurality of dummy channel structures that pass through the stacked structure. Moreover, the semiconductor device includes a contact structure in contact with at least one of the plurality of dummy channel structures adjacent thereto, and in contact with one of the plurality of electrode layers.

Abstract: Provided is a vibration motor driving device that controls a vibration motor. The vibration motor driving device includes: a control signal selection unit configured to receive a second control signal provided from a touch detection unit for detecting a touch input to a touch panel and including information for controlling the vibration motor; and a driving current output unit configured to output a vibration motor driving current for driving the vibration motor according to the second control signal.

Abstract: Exemplary methods of etching semiconductor substrates may include flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having an exposed region of a first silicon-containing material and an exposed region of a second silicon-containing material. The second silicon-containing material may be exposed within a recessed feature defined by the substrate. The methods may include flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include forming a plasma within the processing region of the semiconductor processing chamber to generate plasma effluents of the fluorine-containing precursor and the silicon-containing precursor. The methods may include contacting the substrate with the plasma effluents. The methods may include removing at least a portion of the second silicon-containing material.

Abstract: Disclosed is a transportation container blower for mortality prevention and welfare during livestock transportation, comprising: a body connected to a transportation means and having a space in which livestock is accommodated therein and a first blowing port formed at each of lower portions of both sides thereof to be opened; a blowing path installed at an upper end of the body to be long in a longitudinal direction thereof and having a second blowing port which is in communication with an inside of the body and formed at a lower end or a side surface thereof; and a blowing means installed at the body and connected to the blowing path.

Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Abstract: Processing methods may be performed to form recesses in a semiconductor substrate. The methods may include oxidizing an exposed silicon nitride surface on a semiconductor substrate within a processing region of a semiconductor processing chamber. The methods may include forming an inert plasma within the processing region of the processing chamber. Effluents of the inert plasma may be utilized to modify the oxidized silicon nitride. A remote plasma may be formed from a fluorine-containing precursor to produce plasma effluents. The methods may include flowing the plasma effluents to the processing region of the semiconductor processing chamber. The methods may also include removing the modified oxidized silicon nitride from the semiconductor substrate.

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

Abstract: Systems and methods related to a structured illumination (SI)-based inspection apparatus are described. The SI-based inspection apparatus may be capable of accurately inspecting an inspection object in real time with high resolution, while reducing the loss of light. Also described are an inspection method, and a semiconductor device fabrication method including the SI-based inspection method. The inspection apparatus may include a light source configured to generate and output a light beam, a phase shifting grating (PSG) configured to convert the light beam from the light source into the SI, a beam splitter configured to cause the SI to be incident on an inspection object and output a reflected beam from the inspection object, a stage capable of moving the inspection object and on which the inspection object is arranged, and a time-delayed integration (TDI) camera configured to capture images of the inspection object by detecting the reflected beam.

Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

Abstract: Various embodiments of the present invention relate to a secondary battery. The technical problem to be solved is to provide the secondary battery which can improve the insulation strength of first and second multi-tabs, by forming the first and second multi-tabs of first and second electrode assemblies symmetrically with respect to each other, and also can improve the insulation strength of the first and second multi-tabs by forming an insulating layer on the first and second multi-tabs of the first and second electrode assemblies.

Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.

Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.