Abstract: A three-dimensional semiconductor memory device may include a first stack block including first stacks arranged in a first direction on a substrate, a second stack block including second stacks arranged in the first direction on the substrate, and a separation structure provided on the substrate between the first stack block and the second stack block. The separation structure may include first mold layers and second mold layers, which are stacked in a vertical direction perpendicular to a top surface of the substrate.

Abstract: Embodiments of the invention relate to a secondary battery having symmetric multi-tabs, and the technical problem to be solved is providing a secondary battery capable of increasing the insulation level of first and second multi-tabs by forming the first and second multi-tabs of first and second electrode assemblies to be symmetric to each other. To this end, the present invention provides a secondary battery comprising: a case; a first electrode assembly accommodated inside the case and having first multi-tabs; a second electrode assembly accommodated in parallel with the first electrode assembly inside the case and having second multi-tabs; and a cap plate closing the case and having electrode terminals electrically connected to the first and second multi-tabs of the first and second electrode assemblies, wherein the first and second multi-tabs are formed so as to be symmetrical with respect to the boundary area between the first and second electrode assemblies.

Abstract: The present invention relates to an allulose syrup and method of preparing the same, and more specifically, an allulose syrup with proper viscosity ranges, including viscosity-regulating agent and a dispersant and method of preparing the same.

Abstract: Described herein are aminoquinoline and aminoacridine based hybrids, pharmaceutical compositions and medicaments that include such aminoquinoline and aminoacridine based hybrids, and methods of using such compounds for diagnosing and/or treating infections, neurodegenerative diseases or disorders, inflammation, inflammation associated diseases and disorders, and/or diseases or disorders that are treatable with dopamine agonists such as the restless leg syndrome.

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

Abstract: Disclosed herein are methods of generating induced pluripotent stem cells. The method involves providing a quantity of somatic or non-embryonic cells, contacting the contacting the somatic or non-embryonic cells with a quantity of one or more reprogramming factors and one or more RNA molecules, and culturing the somatic or non-embryonic cells for a period of time sufficient to generate at least one induced pluripotent stem cell. Various reprogramming factors and RNA molecules for use in the methods are disclosed herein. Also disclosed are cell lines and pharmaceutical compositions generated by use of the methods.

Abstract: A three-dimensional semiconductor memory device includes first and second gate stacked structures, disposed on a base substrate, and stacked in a direction perpendicular to a surface of the base plate, the first and second gate stacked structures including gate electrodes spaced apart from each other and stacked; a through region passing through the first and second gate stacked structures and surrounded by the first and second gate stacked structures; and vertical channel structures passing through the first and second gate stacked structures, wherein the first gate stacked structure has first contact pads adjacent to the through region and arranged in a stepped shape, the second gate stacked structure having second contact pads adjacent to the through region and arranged in a stepped shape, at least a portion of the second contact pads overlap the first contact pads on one side of the through region.

Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Abstract: Systems and methods related to a structured illumination (SI)-based inspection apparatus are described. The SI-based inspection apparatus may be capable of accurately inspecting an inspection object in real time with high resolution, while reducing the loss of light. Also described are an inspection method, and a semiconductor device fabrication method including the SI-based inspection method. The inspection apparatus may include a light source configured to generate and output a light beam, a phase shifting grating (PSG) configured to convert the light beam from the light source into the SI, a beam splitter configured to cause the SI to be incident on an inspection object and output a reflected beam from the inspection object, a stage capable of moving the inspection object and on which the inspection object is arranged, and a time-delayed integration (TDI) camera configured to capture images of the inspection object by detecting the reflected beam.

Abstract: Disclosed is an antenna control method and apparatus. The antenna control method includes determining an azimuth angle of an antenna based on ephemeris information of a satellite, determining an elevation angle and a cross level of the antenna based on the azimuth angle and controlling the antenna based on the azimuth angle, the elevation angle, and the cross level.

Abstract: Disclosed herein are a motor assembly and a cleaner having the same. The motor assembly includes a rotor configured to rotate and a stator configured to electromagnetically interact with the rotor. The stator includes a pair of stator bodies disposed to be symmetrical to each other with the rotor in between, each stator body having at least two stator cores arranged in parallel to each other.

Abstract: A three-dimensional semiconductor memory device includes a plurality of first insulating layers vertically stacked on a peripheral logic structure, second insulating layers stacked alternately with the first insulating layers, conductive layers stacked alternately with the first insulating layers and disposed on sidewalls of the second insulating layers, through-interconnections penetrating the first insulating layers and the second insulating layers so as to be connected to the peripheral logic structure, and a first conductive line electrically connected to a plurality of first conductive layers of the conductive layers.

Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

Abstract: Provided is a vibration motor driving device that controls a vibration motor. The vibration motor driving device includes: a control signal selection unit configured to receive a second control signal provided from a touch detection unit for detecting a touch input to a touch panel and including information for controlling the vibration motor; and a driving current output unit configured to output a vibration motor driving current for driving the vibration motor according to the second control signal.

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.

Abstract: A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.

Abstract: Disclosed is a transistor including a substrate, first and second type wells in contact with each other on the substrate; and a breakdown voltage improving region including vertical high concentration doped regions according to first and second types vertically in contact from upper surfaces of the first and second type wells to an upper surface of the substrate in a portion where the first and second type wells are in contact with each other.

Abstract: Three-dimensional semiconductor memory devices are provided. The devices may include a semiconductor layer and electrode structures on the semiconductor layer. The electrode structures may include a first electrode structure including a first electrode portion and a first pad portion and a second electrode structure including a second electrode portion and a second pad portion. Each of the first and second electrode portions has a first width, each of the first and second pad portions has a second width, and the second width may be less than the first width. The first and second electrode portions may be spaced apart from each other by a first distance, and the first and second pad portions may be spaced apart from each other by a second distance that may be greater than the first distance.

Abstract: A semiconductor device comprises a peripheral circuit region provided on a first substrate and including circuit devices and a contact plug extending on the first substrate in a vertical direction; a memory cell region provided on a second substrate disposed above the first substrate and including memory cells; and a through insulating region penetrating through the second substrate on the contact plug and covering an upper surface of the contact plug.

Abstract: A semiconductor memory device includes a peripheral circuit structure including a peripheral circuit insulating layer, a middle connection structure on the peripheral circuit insulating layer, the middle connection structure including a middle connection insulating layer, and a bottom surface of the middle connection insulating layer is in contact with a top surface of the peripheral circuit insulating layer, stack structures on sides of the middle connection structure, and channel structures extending vertically through each of the stack structures, wherein at least one side surface of the middle connection insulating layer is an inclined surface, a lateral sectional area of the middle connection insulating layer decreasing in an upward direction oriented away from the peripheral circuit insulating layer.