Abstract: A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

Abstract: A highly integrated semiconductor memory device includes a substrate, a plurality of vertical pillars above the substrate, a plurality of connection lines extending over the vertical pillars, a plurality of lower via plugs provided above the vertical pillars and connecting the vertical pillars to the connection lines, a dummy connection line provided at a same level as the connection lines with respect to a main surface of the substrate, and a dummy via plug connected to a lower surface of the dummy connection line and having a different height than each of the lower via plugs. The vertical pillars, the connection lines, the lower via plugs are provided in a cell region, and the dummy connection line and the dummy via plug are provided in a dummy region.

Abstract: The present invention relates to a laminate and a device fabricated using the laminate. The laminate includes a first polyimide resin layer between a carrier substrate and a second polyimide resin layer, wherein the first polyimide resin layer has a coefficient of thermal expansion (CTE) equal to or lower than the CTE of the second polyimide-based resin layer at a temperature of 100 to 200° C., and the adhesive strength of the first resin layer to the second resin layer decreases when a physical stimulus causing no chemical changes in the first resin layer is applied to the laminate. According to the present invention, the flexible substrate can be easily separated from the carrier substrate without the need for further processing such as laser or light irradiation. Therefore, the use of the laminate facilitates the fabrication of the device having the flexible substrate. The device may be, for example, a flexible display device.

Abstract: Disclosed is an electronic device in which a defect, where air bubbles occur in an OCR or a gap space is not filled in a D/B process, is prevented and a gap filling tape is adhered to a display module without a gap, thereby solving a problem where a crack or yellowing occurs in the display module. The electronic device includes a display panel including a first substrate and a second substrate bonded to a portion other than one edge of the first substrate, a panel supporting part supporting the display panel, a cover window attached on a front surface of the second substrate, a housing accommodating the panel supporting part and supporting the cover window, a gap between the one edge of the first substrate and the cover window, and a gap sealing member attached on a side surface of the panel supporting part to seal the gap.

Abstract: The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including AlxGa(1-x)N (0<x<1) and a quantum well layer including AlyGa(1-y)N (0<x<y<1), and at least one of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer includes AlGaN. The intermediate layer includes AlN and has a plurality of air voids formed in the AlN. At least some of the air voids are irregularly aligned and the number of the air voids is 107 to 1010/cm2.

Abstract: A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure including pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, extending in a first direction that is parallel to the surface of the substrate, and may include a stair step structure on the connection region, first and second string selection electrodes that extend in the first direction on the electrode structure and spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction. The first and second string selection electrodes may each include an electrode portion on the cell array region and a pad portion that extends from the electrode portion in the first direction and on the connection region.

Abstract: A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction. A first line pattern of the plurality of line patterns may include a wider portion having a second width in a second direction perpendicular to the first direction that is greater than the first width. One or more second line patterns may be located adjacent to the first line pattern and include a conformal portion conformally formed about the wider portion of the first line pattern. One or more third line patterns may be located adjacent to the second line pattern and include an end portion near the conformal portion of the one or more second line pattern.

Abstract: A vertical memory device includes a substrate with a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes parallel to the substrate in the cell array and word line contact regions, the gate electrodes being stacked and spaced apart in a direction perpendicular to the substrate, a channel structure through the gate electrodes in the cell array region, the channel structure being electrically connected to the substrate, a dummy channel structure through the gate electrodes in the word line contact region, the dummy channel structure being spaced apart from the substrate, and a conductive line parallel to the substrate and electrically connected to a first gate electrode, the conductive line crossing at least a portion of an extension of the dummy channel structure in the perpendicular direction.

Abstract: Provided is a vertical NAND flash memory device. The vertical NAND flash memory device may include word lines formed on a substrate, a plurality of pads horizontally extending from the word lines, and contact plugs connected to respective pads. The contact plugs may include a first contact plug connected to a lowermost pad that is closest to the substrate, and a set of second contact plugs each second contact plug connected to a corresponding pad of the plurality of pads. A first distance between the first contact plug and a second contact plug of the set of second contact plugs that is adjacent to the first contact plug may be different from second distances between adjacent contact plugs of the set of second contact plugs. The second distances may be substantially the same as each other.

Abstract: A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

Abstract: A vertical memory device includes a substrate including a cell region and a peripheral circuit region, gate electrodes sequentially stacked on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a channel on the cell region and extending through the gate electrodes in the vertical direction, a first lower contact plug on the peripheral circuit region and extending in the vertical direction, a second lower contact plug on the peripheral circuit region adjacent to the first lower contact plug and extending in the vertical direction, and a first upper wiring electrically connected to the first lower contact plug. The first upper wiring is configured to and apply an electrical signal to the first lower contact plug. The second lower contact plug is not electrically connected to an upper wiring configured to apply an electrical signal.

Abstract: A semiconductor device includes a plurality of line patterns formed apart from one another on a substrate, the plurality of line patterns having a first width and extending parallel to one another in a first direction. A first line pattern of the plurality of line patterns may include a wider portion having a second width in a second direction perpendicular to the first direction that is greater than the first width. One or more second line patterns may be located adjacent to the first line pattern and include a conformal portion conformally formed about the wider portion of the first line pattern. One or more third line patterns may be located adjacent to the second line pattern and include an end portion near the conformal portion of the one or more second line pattern.

Abstract: The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including AlxGa(1-x)N (0<x<1) and a quantum well layer including AlyGa(1-y)N (0<x<y<1), and at least one of the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer includes AlGaN. The intermediate layer includes AlN and has a plurality of air voids formed in the AlN. At least some of the air voids are irregularly aligned and the number of the air voids is 107 to 1010/cm2.

Abstract: This invention relates to a method of evaluating monomers having an effect on copolymer characteristics and a system using the same, and particularly to a novel method of evaluating the magnitude of the effect of monomers on copolymer characteristics, which cannot be evaluated using existing methods. The method of evaluating monomers having an effect on copolymer characteristics and the system using the same are innovative because the extent of changes in copolymer characteristics can be predicted at the monomer level by quantitatively evaluating the effect of the monomers on the copolymer characteristics, taking into consideration the kind or linkage type of monomers.

Abstract: This invention relates to a method of evaluating the identity of polymers and a system using the same, and more particularly to a novel method of evaluating the identity of polymers, wherein the identity of multiple polymers, rather than just one polymer, can be determined using only information about structures of the polymers, without the need to determine the characteristics of synthesized polymers through real-world experimentation. In order to evaluate the identity of polymers, the identity index PohoFactor(Xi) for each of target polymers is developed and used, and the identity of polymers can be accurately determined on a quantitative basis by evaluating correlations between the identity indices for all polymers, the identity of which is to be determined.

Abstract: This invention relates to a method and system for predictively evaluating a water-insoluble material even without solubility measurement experiments.

Abstract: A semiconductor memory device may include an electrode structure including a selection line on a substrate and word lines between the substrate and the selection line, vertical pillars penetrating the electrode structure and being connected to the substrate, sub-interconnections and bit lines sequentially stacked on and electrically connected to the vertical pillars, and lower contacts connecting the vertical pillars to the sub-interconnections. The selection line may include a plurality of selection lines separated from each other in a first direction by an insulating separation layer, and central axes of the lower contacts connected in common to one of the sub-interconnections may be shifted, in a second direction across the first direction and parallel to a top surface of the substrate, from central axes of the vertical pillars thereunder.

Abstract: This invention relates to a method of evaluating the similarity of structural effects of solvents determining solvent reactivity and a system using the same, and more particularly to a novel evaluation method that is able to quantitatively measure the structural effect of a solvent having an influence on reactivity upon reaction of the solvent with a predetermined material and to a system using the same.

Abstract: An electronic device includes a connector, a first communication circuit connected with the connector, a second communication circuit connected with the connector, and a processor. The processor is configured to verify identification information corresponding to an external electronic device connected with the electronic device through the connector, to receive or transmit, if the external electronic device is an electronic device of a first type, data from or to the external electronic device through the first communication circuit and the second communication circuit based on the identification information, and to receive or transmit, if the external electronic device is the electronic device of a second type, data from or to the external electronic device through the first communication circuit based on the identification information.

Abstract: An electronic device is provided. The electronic device includes a first connector including a first pin and a second pin configured to connect with a first external electronic device, a second connector configured to connect with a second external electronic device, a connection sensing circuit configured to sense a connection or disconnection of the second external electronic device coupled to the first pin via the second connector, and a switch configured to supply power received from the first external electronic device via the second pin to the first pin if the disconnection is sensed via the connection sensing circuit.