Patents by Inventor Kyu-Jin Choi

Kyu-Jin Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12206437
    Abstract: The present disclosure relates to a time-division multiplexing (TDM)-based multi-channel electrocardiogram measurement apparatus and method, which remove the influence of power line interference in a way to implement multiple channels by using a TDM method, remove an electrode DC offset (EDO) through a pre-charged capacitor, and periodically take a current out or supply a current. The TDM-based multi-channel electrocardiogram measurement apparatus and method robust against power line interference according to the present disclosure have advantages in that it can measure electrocardiogram by using multiple channels with low power and high integration based on TDM, can perform contactless measurement because an EDO is efficiently eliminated and high impedance is satisfied, and has a characteristic robust against power line interference.
    Type: Grant
    Filed: November 16, 2022
    Date of Patent: January 21, 2025
    Assignee: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jae Yoon Sim, Kyu Jin Choi
  • Publication number: 20240282768
    Abstract: A semiconductor device may include a first capacitor and a second capacitor located at a different height from the first capacitor. Each of the first and second capacitors includes a lower electrode, an upper electrode and a dielectric layer between the lower electrode and the upper electrode. A selected one of the lower and upper electrodes includes a first portion having a cylindrical shape including a closed lower surface and an opened upper surface and a second portion vertically extended from the first portion of the selected one. A selected another one of the lower and upper electrodes includes a first portion having a bar shape extended into the first portion of the selected one, a second portion vertically extended from the first portion of the selected another one, and a third portion having a disc shape between the first portion and the second portion in the selected another one.
    Type: Application
    Filed: April 30, 2024
    Publication date: August 22, 2024
    Inventors: Kyu Jin CHOI, Seong Min MA, Kyu Chan SHIM
  • Publication number: 20240258308
    Abstract: A semiconductor device may include a first capacitor and a second capacitor located at a different height from the first capacitor. Each of the first and second capacitors includes a lower electrode, an upper electrode and a dielectric layer between the lower electrode and the upper electrode. A selected one of the lower and upper electrodes includes a first portion having a cylindrical shape and a second portion vertically extended from the first portion of the selected one. A selected another one of the lower and upper electrodes includes a first portion having a bar shape extended into the first portion of the selected one, a second portion vertically extended from the first portion of the selected another one, and a third having a cylindrical shape between the first portion and the second portion in the selected another one to surround the first portion of the selected one.
    Type: Application
    Filed: April 9, 2024
    Publication date: August 1, 2024
    Inventors: Kyu Jin CHOI, Seong Min MA, Kyu Chan SHIM
  • Patent number: 11984446
    Abstract: A semiconductor device may include a first capacitor and a second capacitor. The first capacitor may include a first lower electrode, a first upper electrode and a first dielectric layer disposed between the first lower electrode and the first upper electrode at a first height. The second capacitor may be positioned spaced apart from the first capacitor. The second capacitor may include a second lower electrode, a second upper electrode and a second dielectric layer disposed between the second lower electrode and the second upper electrode at a second height different from the first height.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: May 14, 2024
    Assignee: SK hynix Inc.
    Inventors: Kyu Jin Choi, Seong Min Ma, Kyu Chan Shim
  • Patent number: 11972946
    Abstract: The present inventive concept relates to a method for removing impurities in thin film and a substrate processing apparatus. The method for removing impurities in a thin film includes the steps of: providing a substrate having a thin film formed thereon in a process chamber; supplying a first gas reacting and coupling with impurities contained in the thin film, into the process chamber; exhausting a coupled product of the impurities and the first gas by depressurizing an interior of the process chamber after stopping the supply of the first gas; curing the thin film by supplying a second gas being different from the first gas into the process chamber; and stopping the supply of the second gas and exhausting the remaining second gas from the interior of the process chamber.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: April 30, 2024
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Kyu Jin Choi, Gyu Ho Choi, Sang Hyuk Hwang
  • Publication number: 20240120938
    Abstract: The present disclosure relates to a time-division multiplexing (TDM)-based multi-channel electrocardiogram measurement apparatus and method, which remove the influence of power line interference in a way to implement multiple channels by using a TDM method, remove an electrode DC offset (EDO) through a pre-charged capacitor, and periodically take a current out or supply a current. The TDM-based multi-channel electrocardiogram measurement apparatus and method robust against power line interference according to the present disclosure have advantages in that it can measure electrocardiogram by using multiple channels with low power and high integration based on TDM, can perform contactless measurement because an EDO is efficiently eliminated and high impedance is satisfied, and has a characteristic robust against power line interference.
    Type: Application
    Filed: November 16, 2022
    Publication date: April 11, 2024
    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION
    Inventors: Jae Yoon SIM, Kyu Jin CHOI
  • Publication number: 20230395369
    Abstract: The disclosed technology generally relates to forming a titanium nitride layer, and more particularly to forming by atomic layer deposition a titanium nitride layer on a seed layer. In one aspect, a semiconductor structure comprises a semiconductor substrate comprising a non-metallic surface. The semiconductor structure additionally comprises a seed layer comprising silicon (Si) and nitrogen (N) conformally coating the non-metallic surface and a TiN layer conformally coating the seed layer. Aspects are also directed to methods of forming the semiconductor structures.
    Type: Application
    Filed: February 15, 2023
    Publication date: December 7, 2023
    Inventors: Sung-Hoon Jung, Niloy Mukherjee, Hee Seok Kim, Kyu Jin Choi, Moonsig Joo, Hae Young Kim, Yoshikazu Okuyama, Nariman Naghibolashrafi, Bunsen B. Nie, Somilkumar J. Rathi
  • Publication number: 20230389305
    Abstract: A semiconductor memory device includes: a first stack structure and a second stack structure on a semiconductor substrate; a first vertical structure having a side all in contact with the first stack structure, the first vertical structure including a first memory layer and a first channel pattern; a second vertical structure having a sidewall in contact with the second stack structure, the second vertical structure including a second memory layer and a second channel pattern; a first bit line contact structure on the first vertical structure; and a first bit line overlapping with the first bit line contact structure. Each of the first stack structure and the second stack structure includes conductive layers stacked on the semiconductor substrate to be spaced apart from each other. The first bit line contact structure has a shape which is widened toward the first bit line.
    Type: Application
    Filed: November 18, 2022
    Publication date: November 30, 2023
    Inventors: Kyu Jin CHOI, Hae Ri KIM, Kyu Chan SHIM
  • Patent number: 11702737
    Abstract: Provided is a batch-type substrate processing apparatus. The substrate processing apparatus includes a vertical reaction tube having an internal space for receiving a substrate boat in which a substrate is stacked in multiple stages, a deposition gas supply unit configured to supply a deposition gas inside the reaction tube, a heater disposed outside the reaction tube to provide a thermal energy inside the reaction tube, and an adhesion layer coated on an inner wall of the reaction tube and to which a deposition by-product layer by an excess deposition gas is attached.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: July 18, 2023
    Inventors: Hee Seok Kim, Kyu Jin Choi, Kang Il Lee
  • Publication number: 20230165861
    Abstract: The present invention provides a pharmaceutical composition for protecting or mitigating radiation against radiation-induced damage, comprising a compound of Formula 1, or a pharmaceutically acceptable salt or solvate thereof. Further, the present invention provides a pharmaceutical composition for preventing or treating pulmonary fibrosis, comprising a compound of Formula 1, or a pharmaceutically acceptable salt or solvate thereof.
    Type: Application
    Filed: December 20, 2018
    Publication date: June 1, 2023
    Inventors: Yoon-Jin LEE, Heang Ran SEO, Hae-Jun LEE, A-Ram KIM, Inhee CHOI, Sunhee KANG, Kyu Jin CHOI
  • Patent number: 11587784
    Abstract: The disclosed technology generally relates to forming a titanium nitride layer, and more particularly to forming by atomic layer deposition a titanium nitride layer on a seed layer. In one aspect, a semiconductor structure comprises a semiconductor substrate comprising a non-metallic surface. The semiconductor structure additionally comprises a seed layer comprising silicon (Si) and nitrogen (N) conformally coating the non-metallic surface and a TiN layer conformally coating the seed layer. Aspects are also directed to methods of forming the semiconductor structures.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: February 21, 2023
    Assignee: Eugenus, Inc.
    Inventors: Sung-Hoon Jung, Niloy Mukherjee, Hee Seok Kim, Kyu Jin Choi, Moonsig Joo, Hae Young Kim, Yoshikazu Okuyama, Nariman Naghibolashrafi, Bunsen B. Nie, Somilkumar J. Rathi
  • Publication number: 20230024352
    Abstract: A semiconductor device may include a first capacitor and a second capacitor. The first capacitor may include a first lower electrode, a first upper electrode and a first dielectric layer disposed between the first lower electrode and the first upper electrode at a first height. The second capacitor may be positioned spaced apart from the first capacitor. The second capacitor may include a second lower electrode, a second upper electrode and a second dielectric layer disposed between the second lower electrode and the second upper electrode at a second height different from the first height.
    Type: Application
    Filed: December 29, 2021
    Publication date: January 26, 2023
    Inventors: Kyu Jin CHOI, Seong Min MA, Kyu Chan SHIM
  • Patent number: 11488845
    Abstract: In accordance with an exemplary embodiment, a substrate processing apparatus includes: a tube assembly having an inner space in which substrates are processed and assembled by laminating a plurality of laminates, each of which includes an injection part and an exhaust hole; a substrate holder configured to support the plurality of substrates in a multistage manner in the inner space; a supply line connected to one injection part of the plurality of laminates to supply a process gas; and an exhaust line connected to one of a plurality of exhaust holes to exhaust the process gas, and the substrate processing apparatus that has a simple structure and induces a laminar flow of the process gas to uniformly supply the process gas to a top surface of the substrate.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: November 1, 2022
    Inventors: Cha Young Yoo, Sung Tae Je, Kyu Jin Choi, Ja Dae Ku, Jun Kim, Bong Ju Jung, Kyung Seok Park, Yong Ki Kim, Jae Woo Kim
  • Patent number: 11431299
    Abstract: A bias circuit includes a current generating circuit generating an internal base current based on a reference current, a bias output circuit generating a base bias current based on the internal base current and outputting the base bias current to an amplifying circuit, and a temperature compensation circuit regulating the base bias current based on a temperature voltage reflecting a change in ambient temperature.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 30, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyu Jin Choi, Je Hee Cho
  • Publication number: 20220230875
    Abstract: The present inventive concept relates to a method for removing impurities in thin film and a substrate processing apparatus. The method for removing impurities in a thin film includes the steps of: providing a substrate having a thin film formed thereon in a process chamber; supplying a first gas reacting and coupling with impurities contained in the thin film, into the process chamber; exhausting a coupled product of the impurities and the first gas by depressurizing an interior of the process chamber after stopping the supply of the first gas; curing the thin film by supplying a second gas being different from the first gas into the process chamber; and stopping the supply of the second gas and exhausting the remaining second gas from the interior of the process chamber.
    Type: Application
    Filed: January 12, 2022
    Publication date: July 21, 2022
    Inventors: Kyu Jin CHOI, Gyu Ho CHOI, Sang Hyuk HWANG
  • Patent number: 11139786
    Abstract: An amplifying device includes a current generating circuit, a bias amplifying circuit, and a compensation circuit. The current generating circuit is configured to generate an internal current based on an internal voltage. The bias amplifying circuit, connected to the current generating circuit, is configured to output a bias current generated by amplifying the internal current to a power amplifying circuit. The compensation circuit, connected to the current generating circuit, is configured to adjust the internal voltage based on a bias voltage of the power amplifying circuit.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: October 5, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Je Hee Cho, Kyu Jin Choi
  • Publication number: 20210104397
    Abstract: The disclosed technology generally relates to forming a titanium nitride layer, and more particularly to forming by atomic layer deposition a titanium nitride layer on a seed layer. In one aspect, a semiconductor structure comprises a semiconductor substrate comprising a non-metallic surface. The semiconductor structure additionally comprises a seed layer comprising silicon (Si) and nitrogen (N) conformally coating the non-metallic surface and a TiN layer conformally coating the seed layer. Aspects are also directed to methods of forming the semiconductor structures.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 8, 2021
    Inventors: Sung-Hoon Jung, Niloy Mukherjee, Hee Seok Kim, Kyu Jin Choi, Moonsig Joo, Hae Young Kim, Yoshikazu Okuyama, Nariman Naghibolashrafi, Bunsen B. Nie, Somilkumar J. Rathi
  • Publication number: 20210102287
    Abstract: The present invention relates to a thin film deposition apparatus and a thin film deposition method in which the resistivity of a thin film is decreased by reducing the content of impurities inside a thin film. The thin film deposition apparatus may include a process chamber configured to perform a deposition process for causing a first metal and a reactant source to react, to form a thin film on a substrate; a source gas nozzle part configured to supply, into the process chamber, a source gas including the first metal and a ligand; a pretreatment gas nozzle part configured to supply, into the process chamber, a pretreatment gas including a second metal reactable with the ligand; and a reaction gas nozzle part configured to supply, into the process chamber, a reaction gas comprising the reactant source.
    Type: Application
    Filed: September 25, 2020
    Publication date: April 8, 2021
    Inventors: Kwang Woon LEE, Kang Il LEE, Kyu Jin CHOI, Min Hyuk IM, Sung Ha CHOI
  • Patent number: 10972056
    Abstract: A bias circuit includes a current generating circuit generating a first compensation current and a second compensation current, in which an ambient temperature change is reflected, based on a reference current, a first temperature compensation circuit generating a first base bias current, based on the first compensation current, to output the first base bias current to a base node of an amplifying circuit, and a second temperature compensation circuit generating a second base bias current, based on the second compensation current, to output the second base bias current to the base node of the amplifying circuit.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: April 6, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kyu Jin Choi, Je Hee Cho
  • Publication number: 20210091731
    Abstract: An amplifying device includes a current generating circuit, a bias amplifying circuit, and a compensation circuit. The current generating circuit is configured to generate an internal current based on an internal voltage. The bias amplifying circuit, connected to the current generating circuit, is configured to output a bias current generated by amplifying the internal current to a power amplifying circuit. The compensation circuit, connected to the current generating circuit, is configured to adjust the internal voltage based on a bias voltage of the power amplifying circuit.
    Type: Application
    Filed: December 24, 2019
    Publication date: March 25, 2021
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Je Hee CHO, Kyu Jin CHOI