Patents by Inventor Kyu Oh Lee

Kyu Oh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200294938
    Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.
    Type: Application
    Filed: March 14, 2019
    Publication date: September 17, 2020
    Inventors: Rahul JAIN, Kyu-Oh LEE, Islam A. SALAMA, Amruthavalli P. ALUR, Wei-Lun K. JEN, Yongki MIN, Sheng C. LI
  • Patent number: 10777514
    Abstract: Techniques are provided for an inductor at a second level interface between a first substrate and a second substrate. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first substrate, second conductive traces of a second non-semiconductor substrate, and a plurality of connectors configured to connect the first substrate with the second substrate. Each connector of the plurality of connectors can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Publication number: 20200273776
    Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.
    Type: Application
    Filed: February 27, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Zhimin Wan, Ying Wang, Yikang Deng, Chong Zhang, Jiwei Sun, Zhenguo Jiang, Kyu-Oh Lee
  • Publication number: 20200266149
    Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.
    Type: Application
    Filed: December 30, 2017
    Publication date: August 20, 2020
    Inventors: Cheng XU, Junnan ZHAO, Ji Yong PARK, Kyu Oh LEE
  • Publication number: 20200251467
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Application
    Filed: April 22, 2020
    Publication date: August 6, 2020
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Publication number: 20200211927
    Abstract: Microelectronic assemblies that include a cooling channel, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a surface, a die having a surface, and a fluidic channel between the surface of the die and the surface of the package substrate, wherein a top surface of the fluidic channel is defined by the surface of the die and a bottom surface of the fluidic channel is defined by the surface of the package substrate. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a surface; and an interposer having a fluidic channel between the surface of the die and the surface of the package substrate.
    Type: Application
    Filed: December 27, 2018
    Publication date: July 2, 2020
    Applicant: Intel Corporation
    Inventors: Zhimin Wan, Cheng Xu, Yikang Deng, Junnan Zhao, Ying Wang, Chong Zhang, Kyu Oh Lee, Chandra Mohan Jha, Chia-Pin Chiu
  • Patent number: 10692847
    Abstract: Discussed generally herein are methods and devices for multichip packages that include an inorganic interposer. A device can include a substrate including low density interconnect circuitry therein, an inorganic interposer on the substrate, the inorganic interposer including high density interconnect circuitry electrically connected to the low density interconnect circuitry, the inorganic interposer including inorganic materials, and two or more chips electrically connected to the inorganic interposer, the two or more chips electrically connected to each other through the high density interconnect circuitry.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Daniel Sobieski, Kristof Darmawikarta, Sri Ranga Sai Boyapati, Merve Celikkol, Kyu Oh Lee, Kemal Aygun, Zhiguo Qian
  • Publication number: 20200185300
    Abstract: An integrated circuit (IC) package comprises a substrate comprising a dielectric and a thermal conduit that is embedded within the dielectric. The thermal conduit has a length that extends laterally within the dielectric from a first end to a second end. An IC die is thermally coupled to the first end of the thermal conduit. The IC die comprises an interconnect that is coupled to the first end of the thermal conduit. An integrated heat spreader comprises a lid over the IC die and at least one sidewall extending from the edge of the lid to the substrate that is thermally coupled to the second end of the thermal conduit.
    Type: Application
    Filed: December 10, 2018
    Publication date: June 11, 2020
    Applicant: INTEL CORPORATION
    Inventors: Cheng Xu, Zhimin Wan, Lingtao Liu, Yikang Deng, Junnan Zhao, Chandra Mohan Jha, Kyu-oh Lee
  • Publication number: 20200168384
    Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.
    Type: Application
    Filed: September 28, 2017
    Publication date: May 28, 2020
    Applicant: Intel Corporation
    Inventors: Junnan Zhao, Ying Wang, Cheng Xu, Kyu Oh Lee, Sheng Li, Yikang Deng
  • Publication number: 20200168569
    Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.
    Type: Application
    Filed: March 30, 2017
    Publication date: May 28, 2020
    Inventors: Sai VADLAMANI, Aleksandar ALEKSOV, Rahul JAIN, Kyu Oh LEE, Kristof Kuwawi DARMAWIKARTA, Robert Alan MAY, Sri Ranga Sai BOYAPATI, Telesphor KAMGAING
  • Patent number: 10643994
    Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Rahul Jain, Seo Young Kim, Kyu Oh Lee, Ji Yong Park, Sai Vadlamani, Junnan Zhao
  • Publication number: 20200119250
    Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate, a die coupled to the substrate, and a thermoelectric device. The thermoelectric device may include a P-type semiconductor material, a N-type semiconductor material, and a plurality of interconnect structures to transmit current through the P-type and N-type semiconductor material. In an example, the P-type semiconductor material and the N-type semiconductor material may be at least in part embedded within the substrate. The thermoelectric device has a first side proximal to the die, and a second side separated from the die by the first side.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Applicant: Intel Corporation
    Inventors: Cheng Xu, Zhimin Wan, Yikang Deng, Junnan Zhao, Chong Zhang, Ying Wang, Kyu-oh Lee
  • Publication number: 20200118990
    Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a cavity, and phase change material within the cavity. In an example, the phase change material has a phase change temperature lower than 120 degree centigrade. A die may be coupled to the substrate. In an example, the semiconductor device package structure includes one or more interconnect structures that are to couple the die to the phase change material within the cavity.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 16, 2020
    Applicant: Intel Corporation
    Inventors: Cheng Xu, Zhimin Wan, Yikang Deng, Junnan Zhao, Chong Zhang, Chandra Mohan M. Jha, Ying Wang, Kyu-oh Lee
  • Publication number: 20200075473
    Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.
    Type: Application
    Filed: May 23, 2017
    Publication date: March 5, 2020
    Applicant: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli, David Unruh, Frank Truong, Kyu Oh Lee, Junnan Zhao, Sri Chaitra Jyotsna Chavali
  • Publication number: 20200066622
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.
    Type: Application
    Filed: August 21, 2018
    Publication date: February 27, 2020
    Inventors: Rahul JAIN, Kyu Oh LEE
  • Publication number: 20200066543
    Abstract: Disclosed herein are cavity structures in integrated circuit (IC) package supports, as well as related methods and apparatuses. For example, in some embodiments, an IC package support may include: a cavity in a dielectric material, wherein the cavity has a bottom and sidewalls; conductive contacts at the bottom of the cavity, wherein the conductive contacts include a first material; a first peripheral material outside the cavity, wherein the first peripheral material is at the sidewalls of the cavity and proximate to the bottom of the cavity, and the first peripheral material includes the first material; and a second peripheral material outside the cavity, wherein the second peripheral material is at the sidewalls of the cavity and on the first peripheral material, and the second peripheral material is different than the first peripheral material.
    Type: Application
    Filed: August 27, 2018
    Publication date: February 27, 2020
    Applicant: Intel Corporation
    Inventors: Rahul Jain, Sai Vadlamani, Junnan Zhao, Ji Yong Park, Kyu Oh Lee, Cheng Xu
  • Publication number: 20200033154
    Abstract: An electronic device is provided and includes a camera configured to obtain an image, and a location information sensor configured to obtain (or sense) a current location of the electronic device. The electronic device further includes a direction information sensor configured to obtain (or sense) direction information about a direction in which the camera obtains the image and a memory configured to store information about the current location. A processor configured to operatively connect with the location information sensor, the direction information sensor, and the memory, may be further configured to obtain map information corresponding to the current location and arrange and display an orientation of the obtained map information with an orientation corresponding to the direction information, The processor may be configured to output the obtained map information together with a live video obtained by the camera.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 30, 2020
    Inventors: Seung Yeon CHUNG, Jong Kyun SHIN, Pragam RATHORE, Ki Hyoung SON, Dong Oh LEE, Kyu Hyung CHOI, Won Sik LEE, Hyun Yeul LEE
  • Publication number: 20200027856
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Application
    Filed: September 27, 2019
    Publication date: January 23, 2020
    Inventors: Rahul JAIN, Ji Yong PARK, Kyu Oh LEE
  • Patent number: 10525566
    Abstract: A chemical mechanical polishing (CMP) method includes preparing a polishing pad, determining a first load to be applied to a conditioning disk during conditioning of the polishing pad and a first indentation depth at which tips of the conditioning disk are inserted into the polishing pad when the first load is applied to the conditioning disk, preparing a conditioning disk, and positioning the conditioning disk on the polishing pad and conditioning a surface of the polishing pad by using the conditioning disk while applying the first load to the conditioning disk.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: January 7, 2020
    Assignees: SAMSUNG ELECTRONICS CO., LTD., EHWA Diamond Industrial Co., Ltd.
    Inventors: Myung-ki Hong, Yung-jun Kim, Sung-oh Park, Hyo-san Lee, Joo-han Lee, Kyu-min Oh, Sun-gyu Park, Seh-kwang Lee, Chan-ki Yang
  • Publication number: 20200006210
    Abstract: A chip package that includes a die coupled to a package substrate. The substrate includes a first ground layer and a dielectric material engaging the first ground layer. A solder resist layer engages the dielectric material and a routing layer is disposed at least partially within the solder resist layer. A second ground layer engages the solder resist layer.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Cheng Xu, Kyu Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park