Patents by Inventor Kyu Oh Lee
Kyu Oh Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250149501Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.Type: ApplicationFiled: January 8, 2025Publication date: May 8, 2025Inventors: Rahul JAIN, Ji Yong PARK, Kyu Oh LEE
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Patent number: 12288744Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.Type: GrantFiled: May 12, 2022Date of Patent: April 29, 2025Assignee: Intel CorporationInventors: Ji Yong Park, Kyu Oh Lee, Yikang Deng, Zhichao Zhang, Liwei Cheng, Andrew James Brown, Cheng Xu, Jiwei Sun
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Patent number: 12224264Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.Type: GrantFiled: October 30, 2023Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
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Patent number: 12224253Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material.Type: GrantFiled: September 20, 2021Date of Patent: February 11, 2025Assignee: Intel CorporationInventors: Xin Ning, Brandon C. Marin, Kyu Oh Lee, Siddharth K. Alur, Numair Ahmed, Brent Williams, Mollie Stewart, Nathan Ou, Cary Kuliasha
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Publication number: 20240421043Abstract: Various embodiments disclosed relate to methods of making hybrid bonds for semiconductor assemblies, such as including substrate, semiconductor dies, and/or interconnects. The present disclosure includes a hybrid bond assembly having a via and a dielectric layer, each of the via and the dielectric layer bonding two or more components to each other.Type: ApplicationFiled: June 19, 2023Publication date: December 19, 2024Inventors: Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Ji Yong Park, Kyu Oh Lee, Sheng Li, Gang Duan, Sameer Paital
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Patent number: 12154715Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.Type: GrantFiled: July 26, 2022Date of Patent: November 26, 2024Assignee: Intel CorporationInventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
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Publication number: 20240186202Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: January 17, 2024Publication date: June 6, 2024Inventors: Rahul JAIN, Kyu Oh LEE, Siddharth K. ALUR, Wei-Lun K. JEN, Vipul V. MEHTA, Ashish DHALL, Sri Chaitra J. CHAVALI, Rahul N. MANEPALLI, Amruthavalli P. ALUR, Sai VADLAMANI
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Patent number: 11942406Abstract: A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than s second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.Type: GrantFiled: June 7, 2022Date of Patent: March 26, 2024Assignee: Intel CorporationInventors: Kyu Oh Lee, Dilan Seneviratne, Ravindranadh T Eluri
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Patent number: 11935805Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 12, 2023Date of Patent: March 19, 2024Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Publication number: 20240063173Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Inventors: Rahul JAIN, Ji Yong PARK, Kyu Oh LEE
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Patent number: 11901115Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.Type: GrantFiled: July 26, 2022Date of Patent: February 13, 2024Assignee: Intel CorporationInventors: Kyu-Oh Lee, Rahul Jain, Sai Vadlamani, Cheng Xu, Ji Yong Park, Junnan Zhao, Seo Young Kim
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Patent number: 11862552Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.Type: GrantFiled: January 3, 2022Date of Patent: January 2, 2024Assignee: Intel CorporationInventors: Sai Vadlamani, Prithwish Chatterjee, Robert A. May, Rahul S. Jain, Lauren A. Link, Andrew J. Brown, Kyu Oh Lee, Sheng C. Li
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Patent number: 11842981Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.Type: GrantFiled: September 3, 2021Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
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Publication number: 20230317642Abstract: A substrate for an electronic device may include a core. The substrate may include a passive electronic component. For instance, the substrate may include a continuous layer of molding material encapsulating the passive electronic component within the core. One or more through vias may extend between a first surface of the core and a second surface of the core. The substrate may include one or more layers coupled with the core. One or more component terminals may facilitate electrical communication between the passive electronic component and one or more of the first layer or the second layer.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Numair Ahmed, Cary Kuliasha, Kyu Oh Lee, Jung Kyu Han
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Patent number: 11735537Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.Type: GrantFiled: June 28, 2022Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
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Publication number: 20230245940Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 12, 2023Publication date: August 3, 2023Applicant: Intel CorporationInventors: Rahul JAIN, Kyu Oh LEE, Siddharth K. ALUR, Wei-Lun K. JEN, Vipul V. MEHTA, Ashish DHALL, Sri Chaitra J. CHAVALI, Rahul N. MANEPALLI, Amruthavalli P. ALUR, Sai VADLAMANI
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Patent number: 11664290Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.Type: GrantFiled: August 27, 2021Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
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Patent number: 11651885Abstract: Described herein are magnetic core inductors (MCI) and methods for manufacturing magnetic core inductors. A first embodiment of the MCI can be a snake-configuration MCI. The snake-configuration MCI can be formed by creating an opening in a base material, such as copper, and providing a nonconductive magnetic material in the opening. The inductor can be further formed by forming plated through holes into the core material. The conductive elements for the inductor can be formed in the plated through holes. The nonconductive magnetic material surrounds each conductive element and plated through hole. In embodiments, a layered coil inductor can be formed by drilling a laminate to form a cavity through the laminate within the metal rings of the layered coil inductor. The nonconductive magnetic material can be provided in the cavity.Type: GrantFiled: September 28, 2017Date of Patent: May 16, 2023Assignee: Intel CorporationInventors: Junnan Zhao, Ying Wang, Cheng Xu, Kyu Oh Lee, Sheng Li, Yikang Deng
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Publication number: 20230092492Abstract: Transmission pathways in substrates, and associated methods are shown. Example transmission pathways include a semiconductor substrate with a core, a dielectric layer fixed on the core, at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core. The first pathway includes a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway, at least one second electrical transmission pathway extending through the magnetic material, a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway, a copper layer disposed on at least the nickel layer within the second electrical transmission pathway. The dielectric spacer or the nickel layer separates the copper layer from the magnetic material.Type: ApplicationFiled: September 20, 2021Publication date: March 23, 2023Inventors: Xin Ning, Brandon C. Marin, Kyu Oh Lee, Siddharth K. Alur, Numair Ahmed, Brent Williams, Mollie Stewart, Nathan Ou, Cary Kuliasha
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Patent number: 11610706Abstract: A substrate for an integrated circuit package, the substrate comprising a dielectric, at least one conductor plane within the dielectric, and a planar magnetic structure comprising an organic magnetic laminate embedded within the dielectric, wherein the planar magnetic structure is integrated within the at least one conductor plane.Type: GrantFiled: January 12, 2018Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Sai Vadlamani, Prithwish Chatterjee, Rahul Jain, Kyu Oh Lee, Sheng C. Li, Andrew J. Brown, Lauren A. Link