Patents by Inventor KYU OH

KYU OH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SUBSTRATE ASSEMBLY WITH ENCAPSULATED MAGNETIC FEATURE
    Publication number: 20220359115
    Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Kyu-Oh LEE, Rahul JAIN, Sai VADLAMANI, Cheng XU, Ji Yong PARK, Junnan ZHAO, Seo Young KIM
  • M13 mutant for increasing production of DNA
    Patent number: 11492602
    Abstract: The present invention provides a gene including an M13 p5 expressing cassette, which includes a promoter, a ribosome binding site (RBS) and a protein 5 (p5) coding region, wherein at least one base of sequences between the RBS and the p5 coding region is mutated. Using this gene may increase production of single-stranded DNA.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 8, 2022
    Assignee: Korea University Research and Business Foundation
    Inventors: Min Kyu Oh, Dong June Ahn, Seungwoo Lee, Bo Young Lee, Jun Min Lee, Jae Won Lee
  • PORTABLE HOOD
    Publication number: 20220341598
    Abstract: A portable hood may include a base, a head, a column, and a fan. The head may introduce air thereinto and discharge the introduced air to the outside. The column may be coupled eccentrically to a side of the head in a horizontal direction. Further, the fan may be located inside of the head such that the fan is eccentric to the head toward the column.
    Type: Application
    Filed: January 21, 2022
    Publication date: October 27, 2022
    Inventors: Taeyun Lee, Yu Na Jo, Deukwon Lee, Sang Yoon Lee, Min Kyu Oh
  • Thermal management solutions for integrated circuit packages
    Patent number: 11482471
    Abstract: An integrated circuit package may be formed having a heat transfer fluid chamber, wherein the heat transfer fluid chamber may be positioned to allow a heat transfer fluid to directly contact an integrated circuit device within the integrated circuit package. In one embodiment, a first surface of the integrated circuit device may be electrically attached to a first substrate. The first substrate may then may be electrically attached to a second substrate, such that the integrated circuit device is between the first substrate and the second substrate. The second substrate may include a cavity, wherein the heat transfer fluid chamber may be formed between a second surface of the integrated circuit device and the cavity of the second substrate. Thus, at least a portion of a second surface of the integrated circuit device is exposed to the heat transfer fluid which flows into the heat transfer fluid chamber.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: October 25, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Junnan Zhao, Zhimin Wan, Ying Wang, Yikang Deng, Chong Zhang, Jiwei Sun, Zhenguo Jiang, Kyu-Oh Lee
  • METHODS TO EMBED MAGNETIC MATERIAL AS FIRST LAYER ON CORELESS SUBSTRATES AND CORRESPONDING STRUCTURES
    Publication number: 20220328431
    Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Inventors: Cheng XU, Kyu-Oh LEE, Junnan ZHAO, Rahul JAIN, Ji Yong PARK, Sai VADLAMANI, Seo Young KIM
  • METHOD OF PRODUCING ACRYLONITRILE DIMER
    Publication number: 20220306571
    Abstract: The present invention relates to a method of producing an acrylonitrile dimer, the method including: feeding an acrylonitrile monomer, a nonpolar solvent, an alcohol solvent, and a phosphorus-based catalyst to a dimerization reactor to perform a dimerization reaction and reaction product to a distillation column; feeding the acrylonitrile monomer, the nonpolar solvent, and the alcohol solvent from the distillation column to the dimerization reactor; feeding an acrylonitrile dimer and the phosphorus-based catalyst from the distillation column to an extraction device; oxidizing the phosphorus-based catalyst by feeding water including an acid component to the extraction device to inactivate the phosphorus-based catalyst; and separating the inactivated phosphorus-based catalyst and the acrylonitrile dimer.
    Type: Application
    Filed: October 14, 2020
    Publication date: September 29, 2022
    Inventors: Sae Hume Park, Ji Ha Kim, Yu Jin An, Wan Kyu Oh, Hyun Chul Jung, Jeong Heon Ahn
  • SEMICONDUCTOR PACKAGES WITH EMBEDDED INTERCONNECTS
    Publication number: 20220302005
    Abstract: A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than s second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Kyu Oh Lee, Dilan Seneviratne, Ravindranadh T. Eluri
  • METHOD OF PREPARING ACRYLONITRILE DIMER
    Publication number: 20220298104
    Abstract: Provided is a method of preparing an acrylonitrile dimer including: supplying an acrylonitrile monomer, a phosphorus-based catalyst, and an alcohol solvent to a reactor to perform a dimerization reaction to produce dimerized reactants (S10); cooling the dimerized reactants to crystallize the phosphorus-based catalyst (S20); separating the crystallized phosphorus-based catalyst (S30); and supplying the dimerized reactants from which the phosphorus-based catalyst is separated to a distillation column to separate the acrylonitrile dimer (S40).
    Type: Application
    Filed: August 19, 2020
    Publication date: September 22, 2022
    Inventors: Yu Jin AN, Wan Kyu OH, Ji Ha KIM, Hyun Chul JUNG, Sae Hume PARK, Jeong Heon AHN
  • Active purge system for hybrid vehicle and active purge method for hybrid vehicle
    Patent number: 11448167
    Abstract: The present disclosure relates to an active purge system and an active purge method for a hybrid vehicle, and changes a control method for the throughput of the evaporation gas according to the engine torque according to a change in an optimal operating line, the system efficiency, or the state of charge (SOC) condition of a battery using an active purge unit for pressing the evaporation gas generated by a fuel tank and supplying the pressed evaporation gas to an intake pipe, thereby efficiently purging the evaporation gas.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: September 20, 2022
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Young-Kyu Oh, Keum-Jin Park
  • Methods to selectively embed magnetic materials in substrate and corresponding structures
    Patent number: 11450471
    Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 20, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
  • Substrate assembly with encapsulated magnetic feature
    Patent number: 11443892
    Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: September 13, 2022
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Rahul Jain, Sai Vadlamani, Cheng Xu, Ji Yong Park, Junnan Zhao, Seo Young Kim
  • PORTABLE AIR FLOW APPARATUS
    Publication number: 20220282874
    Abstract: A portable air flow apparatus may include a base configured to be seated on a surface, a head comprising a suction inlet through which air is suctioned into the head and a discharge outlet through which the air suctioned in through the suction inlet is discharged, the suction inlet and the discharge outlet being horizontally spaced apart from each other at a right angle with respect to a vertical direction, and a column that connects the head and the base in such a manner that the head is vertically spaced from the base.
    Type: Application
    Filed: January 26, 2022
    Publication date: September 8, 2022
    Inventors: Yu Na JO, Deukwon LEE, Taeyun LEE, Hyunbyung CHA, Sang Yoon LEE, Min Kyu OH, Byunghoon PARK, Yeon A JO, Chang On LEE, Jihye LEE
  • MICROELECTRONIC ASSEMBLIES HAVING CONDUCTIVE STRUCTURES WITH DIFFERENT THICKNESSES ON A CORE SUBSTRATE
    Publication number: 20220278038
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a core substrate with a first conductive structure having a first thickness on the core substrate, and a second conductive structure having a second thickness on the core substrate, where the first thickness is different than the second thickness.
    Type: Application
    Filed: May 12, 2022
    Publication date: September 1, 2022
    Applicant: Intel Corporation
    Inventors: Ji Yong Park, Kyu Oh Lee, Yikang Deng, Zhichao Zhang, Liwei Cheng, Andrew James Brown, Cheng Xu, Jiwei Sun
  • Methods for attaching large components in a package substrate for advanced power delivery
    Patent number: 11432405
    Abstract: A package substrate is disclosed. The package substrate includes a substrate core, a cavity below the substrate core that extends from a surface of a first resist layer to a bottom surface of the package substrate, and a first terminal and a second terminal in the first resist layer. The package substrate also includes one or more passive components that are coupled inside the cavity to the first terminal and the second terminal.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Prithwish Chatterjee, Kyu-oh Lee
  • Methods to embed magnetic material as first layer on coreless substrates and corresponding structures
    Patent number: 11417614
    Abstract: Embodiments include an electronic package that includes a first layer that comprises a dielectric material and a second layer over the first layer, where the second layer comprises a magnetic material. In an embodiment, a third layer is formed over the second layer, where the third layer comprises a dielectric material. In an embodiment, the third layer entirely covers a first surface of the second layer. In an embodiment a first conductive layer and a second conductive layer are embedded within the second layer. In an embodiment, sidewalls of the first conductive layer and the second conductive layer are substantially vertical.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: August 16, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Kyu-Oh Lee, Junnan Zhao, Rahul Jain, Ji Yong Park, Sai Vadlamani, Seo Young Kim
  • ACTIVE PURGE SYSTEM AND PURGING METHOD ACCORDING TO OPERATING STATE OF HYBRID VEHICLE
    Publication number: 20220252016
    Abstract: An active purge system (APS) according to a driving state of a hybrid vehicle includes an active purge unit (APU) configured to pressurize a vaporized gas generated in a fuel tank of the hybrid vehicle and supply the pressurized vaporized gas to an intake pipe, and a control unit configured to control the APU, where the control unit gradually controls a processing amount of the vaporized gas according to the driving state of the hybrid vehicle. The processing amount of the vaporized gas is gradually controlled using the APS according to the driving state of the hybrid vehicle, particularly, a number of places at which slip occurs in a power transmission system of the hybrid vehicle so that degradation of driving ability due to the occurrence of slip is reduced.
    Type: Application
    Filed: August 12, 2021
    Publication date: August 11, 2022
    Inventors: Young-Kyu Oh, Keum-Jin Park
  • Methods to incorporate thin film capacitor sheets (TFC-S) in the build-up films
    Patent number: 11410921
    Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a plurality of build-up layers. In an embodiment, the build-up layers comprise conductive traces and vias. In an embodiment, the electronics package further comprises a capacitor embedded in the plurality of build-up layers. In an embodiment, the capacitor comprises: a first electrode, a high-k dielectric layer over portions of the first electrode, and a second electrode over portions of the high-k dielectric layer.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: August 9, 2022
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee
  • TECHNIQUES FOR AN INDUCTOR AT A FIRST LEVEL INTERFACE
    Publication number: 20220230800
    Abstract: Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.
    Type: Application
    Filed: April 5, 2022
    Publication date: July 21, 2022
    Inventors: Cheng Xu, Yikang Deng, Kyu Oh Lee, Ji Yong Park, Srinivas Venkata Ramanuja Pietambaram, Ying Wang, Chong Zhang, Rui Zhang, Junnan Zhao
  • Semiconductor packages with embedded interconnects
    Patent number: 11393745
    Abstract: A semiconductor package may include a semiconductor package first side, an embedded bridge interconnect, a first via, and a second via. The bridge interconnect may include a bridge interconnect first side with a conductive pad and a bridge interconnect second side. The distance between the bridge interconnect first side and the semiconductor package first side may be less than a distance between the bridge interconnect second side and the semiconductor package first side. The first and second vias may each include a first end that is narrower than a second end. The semiconductor package first side may be closer to the first end of the first via than the second end of the first via, and closer to the second end of the second via than the first end of the second via. The first side of the semiconductor package may be configured to electrically couple to a die.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Kyu Oh Lee, Dilan Seneviratne, Ravindranadh T Eluri
  • Phase change material in substrate cavity
    Patent number: 11387224
    Abstract: A semiconductor device package structure is provided. The semiconductor device package structure includes a substrate having a cavity, and phase change material within the cavity. In an example, the phase change material has a phase change temperature lower than 120 degree centigrade. A die may be coupled to the substrate. In an example, the semiconductor device package structure includes one or more interconnect structures that are to couple the die to the phase change material within the cavity.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Cheng Xu, Zhimin Wan, Yikang Deng, Junnan Zhao, Chong Zhang, Chandra Mohan M Jha, Ying Wang, Kyu-oh Lee