Patents by Inventor Lan Lin

Lan Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer Bonding Process and Structure
    Publication number: 20160358882
    Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
    Type: Application
    Filed: August 16, 2016
    Publication date: December 8, 2016
    Inventors: Ping-Yin Liu, Lan-Lin Chao, Cheng-Tai Hsiao, Xin-Hua Huang, Hsun-Chung Kuang
  • Multiple Swivel Arm Design in Hybrid Bonder
    Publication number: 20160351422
    Abstract: An apparatus for cleaning a wafer includes a wafer station configured to hold the wafer, and a first and a second dispensing system. The first dispensing system includes a first swivel arm, and a first nozzle on the first swivel arm, wherein the first swivel arm is configured to move the first nozzle over and aside of the wafer. The first dispensing system includes first storage tank connected to the first nozzle, with the first nozzle configured to dispense a solution in the first storage tank. The second dispensing system includes a second swivel arm, and a second nozzle on the second swivel arm, wherein the second swivel arm is configured to move the second nozzle over and aside of the wafer. The second dispensing system includes a second storage tank connected to the second nozzle, with the second nozzle configured to dispense a solution in the second storage tank.
    Type: Application
    Filed: July 1, 2016
    Publication date: December 1, 2016
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Lan-Lin Chao
  • Debonding schemes
    Patent number: 9508586
    Abstract: A method includes receiving a wafer stack having at least two wafers bonded together. At least one blade is inserted between a first wafer of the at least two wafers and a second wafer of the at least two wafers. The blade has a channel configured to inject air or fluid. The first wafer is debonded from the second wafer using the at least one blade. In another embodiment, a detacher having a convex bottom surface is attached to the wafer stack. The first wafer is debonded from the second wafer using the detacher.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Lan-Lin Chao, Chia-Shiung Tsai
  • Air trench in packages incorporating hybrid bonding
    Patent number: 9502396
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Hsun-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Apparatus and method for verification of bonding alignment
    Patent number: 9478471
    Abstract: Presented herein is a device comprising a common node disposed in a first wafer' a test node disposed in a first wafer and having a plurality of test pads exposed at a first surface of the first wafer. The test node also has test node lines connected to the test pads and that are separated by a first spacing and extend to a second surface of the first wafer. A comb is disposed in a second wafer and has a plurality of comb lines having a second spacing different from the first spacing. Each of the comb lines has a first surface exposed at a first side of the second wafer. The comb lines provide an indication of an alignment of the first wafer and second wafer by a number or arrangement of connections made by the plurality of comb lines between the test node lines and the common node.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: October 25, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Lan-Lin Chao
  • Method and Apparatus for Image Sensor Packaging
    Publication number: 20160307944
    Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond pad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding strength between the sensor and the ASIC.
    Type: Application
    Filed: June 27, 2016
    Publication date: October 20, 2016
    Inventors: Szu-Ying Chen, Ping-Yin Liu, Calvin Yi-Ping Chao, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung, Lan-Lin Chao
  • Semiconductor having a high aspect ratio via
    Patent number: 9472504
    Abstract: The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: October 18, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Chih Hsieh, Li-Cheng Chu, Ming-Tung Wu, Ping-Yin Liu, Lan-Lin Chao, Chia-Shiung Tsai
  • Biological Sensing Structures
    Publication number: 20160299068
    Abstract: A biological sensing structure includes a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to the top surface. The biological sensing structure includes a first light reflecting layer over the top surface and the sidewall surface of the mesa. The biological sensing structure includes a filling material surrounding the mesa, wherein the mesa protrudes from the filling material. The biological sensing structure includes a stop layer over the filling material and a portion of the first light reflecting layer. The biological sensing structure includes a second light reflecting layer over a portion of the stop layer and a portion of the top surface of the mesa. The biological sensing structure includes an opening in the second light reflecting layer to partially expose the top surface of the mesa.
    Type: Application
    Filed: June 23, 2016
    Publication date: October 13, 2016
    Inventors: Hung-Hua Lin, Li-Cheng Chu, Ming-Tung Wu, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai
  • Integrate rinse module in hybrid bonding platform
    Patent number: 9446467
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: September 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Xin-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Air trench in packages incorporating hybrid bonding
    Patent number: 9443796
    Abstract: A package component includes a surface dielectric layer including a planar top surface, a metal pad in the surface dielectric layer and including a second planar top surface level with the planar top surface, and an air trench on a side of the metal pad. The sidewall of the metal pad is exposed to the air trench.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chen-Jong Wang, Ping-Yin Liu, Jung-Kuo Tu, Tsung-Te Chou, Xin-Hua Huang, Xin-Chung Kuang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Metal-organic framework polymer for solid-phase microextraction
    Patent number: 9421517
    Abstract: A metal-organic framework (MOF) polymer for solid-phase microextraction (SPME) includes an MOF including metal ions building units coordinating polytopic organic linkers; and a polymer coordinatively bonding to the MOF, wherein the polymer is composed of one or more vinyl monomers and a cross-linker those are polymerized in the presence of a radical initiator. A method for preparing a stationary phase for SPME is also provided.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: August 23, 2016
    Assignee: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Hsi-Ya Huang, Chia-Her Lin, Chen-Lan Lin, Yung-Han Shih, Stephen Lirio, Ya-Ting Chen
  • Wafer bonding process and structure
    Patent number: 9425155
    Abstract: A semiconductor device and a method of fabricating the same are introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and one or more conductive pads are formed in the recesses. One or more barrier layers are formed between the passivation layers and the conductive pads. The conductive pads of the first substrate are aligned to the conductive pads of a second substrate and are bonded using a direct bonding method.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ping-Yin Liu, Hsun-Chung Kuang, Cheng-Tai Hsiao, Xin-Hua Huang, Lan-Lin Chao
  • SELF-REMOVAL ANTI-STICTION COATING FOR BONDING PROCESS
    Publication number: 20160229693
    Abstract: A bond free of an anti-stiction layer and bonding method is disclosed. An exemplary method includes forming a first bonding layer; forming an interlayer over the first bonding layer; forming an anti-stiction layer over the interlayer; and forming a liquid from the first bonding layer and interlayer, such that the anti-stiction layer floats over the first bonding layer. A second bonding layer can be bonded to the first bonding layer while the anti-stiction layer floats over the first bonding layer, such that a bond between the first and second bonding layers is free of the anti-stiction layer.
    Type: Application
    Filed: December 9, 2014
    Publication date: August 11, 2016
    Inventors: Ping-Yin Liu, Li-Cheng Chu, Hung-Hua Lin, Shang-Ying Tsai, Yuan-Chih Hsieh, Jung-Huei Peng, Lan-Lin Chao, Chia-Shiung Tsai, Chun-Wen Cheng
  • Method and apparatus for image sensor packaging
    Patent number: 9412725
    Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond bad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding between the sensor and the ASIC.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Ping-Yin Liu, Calvin Yi-Ping Chao, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung, Lan-Lin Chao
  • Apparatus and method for backside illuminated image sensors
    Patent number: 9406711
    Abstract: A backside illuminated image sensor comprises a photodiode and a first transistor located in a first substrate, wherein the first transistor is electrically coupled to the photodiode. The backside illuminated image sensor further comprises a plurality of logic circuits formed in a second substrate, wherein the second substrate is stacked on the first substrate and the logic circuit are coupled to the first transistor through a plurality of bonding pads.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: August 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung, Ping-Yin Liu, Lan-Lin Chao
  • Manufacturing method for stiffened diaphragm and the manufactured diaphragm using same
    Patent number: 9402134
    Abstract: A stiffened diaphragm manufacturing method and the manufactured diaphragm using same are provided. The manufacturing method includes the steps of: applying a hot glue layer to a side of a stiffened plate; putting a base layer on the hot glue layer, and then heating and adhering the base layer and the stiffened plate together; and performing a pressing process on the base layer and the stiffened plate to form a diaphragm having a central portion and a surround portion. The stiffened plate is coated uniformly with the hot glue layer and then put on the base layer to undergo heating and adhesion; hence, an oversupply or undersupply of a glue will be unlikely to happen. Furthermore, the manufacturing process is simple and attains high-strength adhesion between the stiffened plate and the base layer.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: July 26, 2016
    Assignee: MERRY ELECTRONICS (SUZHOU) CO., LTD.
    Inventors: Chen-Mao Yang, Ching-Lan Lin, Po-Yu Chen, Yi-Lin Hsieh, Feng-Min Lai
  • METAL-ORGANIC FRAMEWORK POLYMER FOR SOLID-PHASE MICROEXTRACTION
    Publication number: 20160208047
    Abstract: A metal-organic framework (MOF) polymer for solid-phase microextraction (SPME) includes an MOF including metal ions building units coordinating polytopic organic linkers; and a polymer coordinatively bonding to the MOF, wherein the polymer is composed of one or more vinyl monomers and a cross-linker those are polymerized in the presence of a radical initiator. A method for preparing a stationary phase for SPME is also provided.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 21, 2016
    Inventors: Hsi-Ya Huang, Chia-Her Lin, Chen-Lan Lin, Yung-Han Shih, Stephen Lirio, Ya-Ting Chen
  • Multiple swivel arm design in hybrid bonder
    Patent number: 9385010
    Abstract: An apparatus for cleaning a wafer includes a wafer station configured to hold the wafer, and a first and a second dispensing system. The first dispensing system includes a first swivel arm, and a first nozzle on the first swivel arm, wherein the first swivel arm is configured to move the first nozzle over and aside of the wafer. The first dispensing system includes first storage tank connected to the first nozzle, with the first nozzle configured to dispense a solution in the first storage tank. The second dispensing system includes a second swivel arm, and a second nozzle on the second swivel arm, wherein the second swivel arm is configured to move the second nozzle over and aside of the wafer. The second dispensing system includes a second storage tank connected to the second nozzle, with the second nozzle configured to dispense a solution in the second storage tank.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: July 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Lan-Lin Chao
  • Method and apparatus for image sensor packaging
    Patent number: 9379093
    Abstract: Methods and apparatus for packaging a backside illuminated (BSI) image sensor or a sensor device with an application specific integrated circuit (ASIC) are disclosed. According to an embodiment, a sensor device may be bonded together face-to-face with an ASIC without using a carrier wafer, where corresponding bond pads of the sensor are aligned with bond pads of the ASIC and bonded together, in a one-to-one fashion. A column of pixels of the sensor may share a bond bad connected by a shared inter-metal line. The bond pads may be of different sizes and configured in different rows to be disjoint from each other. Additional dummy pads may be added to increase the bonding between the sensor and the ASIC.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Ping-Yin Liu, Calvin Yi-Ping Chao, Tzu-Jui Wang, Jen-Cheng Liu, Dun-Nian Yaung, Lan-Lin Chao
  • Biological sensing structures
    Patent number: 9377401
    Abstract: A biological sensing structure includes a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to the top surface. The biological sensing structure includes a first light reflecting layer over the top surface and the sidewall surface of the mesa. The biological sensing structure includes a filling material surrounding the mesa, wherein the mesa protrudes from the filling material. The biological sensing structure includes a stop layer over the filling material and a portion of the first light reflecting layer. The biological sensing structure includes a second light reflecting layer over a portion of the stop layer and a portion of the top surface of the mesa. The biological sensing structure includes an opening in the second light reflecting layer to partially expose the top surface of the mesa.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Hua Lin, Li-Cheng Chu, Ming-Tung Wu, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai