Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Abstract: In some embodiments, a method of processing a substrate disposed within a processing volume of a hot wire chemical vapor deposition (HWCVD) process chamber, includes: (a) providing a carbon containing precursor gas into the processing volume, the carbon containing precursor gas being provided into the processing volume from an inlet located a first distance above a surface of the substrate; (b) breaking hydrogen-carbon bonds within molecules of the carbon containing precursor via introduction of hydrogen radicals to the processing volume to deposit a flowable carbon layer atop the substrate, wherein the hydrogen radicals are formed by flowing a hydrogen containing gas over a plurality of filaments disposed within the processing volume above the substrate and the inlet.

Abstract: In some embodiments, a method of processing a substrate disposed within a processing volume of a hot wire chemical vapor deposition (HWCVD) process chamber, includes: (a) providing a silicon containing precursor gas into the processing volume, the silicon containing precursor gas is provided into the processing volume from an inlet located a first distance above a surface of the substrate; (b) breaking hydrogen-silicon bonds within molecules of the silicon containing precursor via introduction of hydrogen radicals to the processing volume to deposit a flowable silicon containing layer atop the substrate, wherein the hydrogen radicals are formed by flowing a hydrogen containing gas over a plurality of wires disposed within the processing volume above the substrate and the inlet.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Abstract: In some embodiments, an inline substrate processing tool may include a substrate carrier having a plurality of slots configured to retain a plurality of substrates parallel to each other when disposed in the slots, a first substrate processing module and a second substrate processing module disposed in a linear arrangement, wherein each substrate processing module includes an enclosure and a track that supports the substrate carrier and provides a path for the substrate carrier to move linearly through the first and second substrate processing modules, and a first gas cap disposed between the first and second substrate processing modules, wherein the first gas cap includes a first process gas conduit to provide a first process gas to the first substrate processing module, and a second process gas conduit to provide a second process gas to the second substrate processing module.

Abstract: A substrate carrier for an epitaxy chamber is described that has an elongated base member supporting two substrate supports in an angled relationship and a center substrate support between the two substrate supports. The center substrate support has one or more openings at which a substrate is positioned for processing, enabling both sides of the substrate to be processed concurrently.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.

Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Abstract: Embodiments described herein generally relate to a batch processing chamber. The batch processing chamber includes a lid, a chamber wall and a bottom that define a processing region. A cassette including a stack of susceptors for supporting substrates is disposed in the processing region. The edge of the cassette is coupled to a plurality of shafts and the shafts are coupled to a rotor. During operation, the rotor rotates the cassette to improve deposition uniformity. A heating element is disposed on the chamber wall and a plurality of gas inlets is disposed through the heating element on the chamber wall. Each gas inlet is substantially perpendicular to the chamber wall.

Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Abstract: An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×1018 dopant atoms per cm3. A threshold voltage set region is formed by placement of a threshold voltage offset plane positioned above the screening region. The threshold voltage set region may be formed by delta doping and have a thickness between Lg/5 and Lg/1 The structure uses minimal or no halo implants to maintain channel dopant concentration at less than 5×1017 dopant atoms per cm3.

Abstract: A method of fabricating a semiconductor device includes providing a substrate having a semiconducting surface and forming a first epitaxial layer on the semiconducting surface. The first epitaxial layer includes a first semiconducting material doped in-situ with at least one dopant of a first conductivity type. The method also includes adding at least one dopant of a second conductivity type into one portion of the substrate to define at least one counter-doped region with an overall doping of the second conductivity type and at least one other region with an overall doping of the first conductivity type in the other portions of substrate. The method further includes forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer being a second semiconducting material that is substantially undoped.

Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.

Abstract: Methods for processing substrates are provided herein. In some embodiments, the method includes providing a substrate supported on a starting template; adhering a first superstrate to a first side of the substrate; separating the substrate with the superstrate from the starting template; determining if a useful life of the used template has been reached; and re-using the used template as a starting template if the useful life has not been reached.

Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.