Abstract: Methods for processing substrates are provided herein. In some embodiments, the method includes providing a substrate supported on a starting template; adhering a first superstrate to a first side of the substrate; separating the substrate with the superstrate from the starting template; determining if a useful life of the used template has been reached; and re-using the used template as a starting template if the useful life has not been reached.

Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.

Abstract: A method for fabricating a semiconductor structure so as to have reduced junction leakage is disclosed. The method includes providing substitutional boron in a semiconductor substrate. The method includes preparing the substrate using a pre-amorphization implant and a carbon implant followed by a recrystallization step and a separate defect repair/activation step. Boron is introduced to the pre-amorphized region preferably by ion implantation.

Abstract: Structures and processes are provided that can be used for effectively integrating different transistor designs across a process platform. In particular, a bifurcated process is provided in which dopants and other processes for forming some transistor types may be performed prior to STI or other device isolation processes, and other devices may be formed thereafter. Thus, doping and other steps and their sequence with respect to the STI process can be selected to be STI-first or STI-last, depending on the device type to be manufactured, the range of device types that are manufactured on the same wafer or die, or the range of device types that are planned to be manufactured using the same or similar mask sets.

Abstract: The present disclosure provides methods and structures for measurement, control, and monitoring the thickness of thin film layers formed as part of a semiconductor manufacturing process. The methods and structures presented provide the capability to measure and monitor the thickness of the thin film using trench line structures. In certain embodiments, the thin film thickness measurement system can be integrated with thin film growth and control software, providing automated process control (APC) or statistical process control (SPC) capability by measuring and monitoring the thin film thickness during manufacturing. Methods for measuring the thickness of thin films can be important to the fabrication of integrated circuits because the thickness and uniformity of the thin film can determine electrical characteristics of the transistors being fabricated.

Abstract: Silicon loss prevention in a substrate during transistor device element manufacture is achieved by limiting a number of photoresist mask and chemical oxide layer stripping opportunities during the fabrication process. This can be achieved through the use of a protective layer that remains on the substrate during formation and stripping of photoresist masks used in identifying the implant areas into the substrate. In addition, undesirable reworking steps due to photoresist mask misalignment are eliminated or otherwise have no effect on consuming silicon from the substrate during fabrication of device elements. In this manner, device elements with the same operating characteristics and performance can be consistently made from lot to lot.

Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.

Abstract: A semiconductor transistor structure fabricated on a silicon substrate effective to set a threshold voltage, control short channel effects, and control against excessive junction leakage may include a transistor gate having a source and drain structure. A highly doped screening region lies is embedded a vertical distance down from the surface of the substrate. The highly doped screening region is separated from the surface of the substrate by way of a substantially undoped channel layer which may be epitaxially formed. The source/drain structure may include a source/drain extension region which may be raised above the surface of the substrate. The screening region is preferably positioned to be located at or just below the interface between the source/drain region and source/drain extension portion. The transistor gate may be formed below a surface level of the silicon substrate and either above or below the heavily doped portion of the source/drain structure.

Abstract: A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion, implantation.

Abstract: A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element.

Abstract: Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.

Abstract: A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a substantially undoped channel layer includes forming an in-situ epitaxial carbon doped silicon substrate that is doped to form the screen layer in the carbon doped silicon substrate and forming the substantially undoped silicon layer above the carbon doped silicon substrate. The method may include implanting carbon below the screen layer and forming a thin layer of in-situ epitaxial carbon doped silicon above the screen layer. The screen layer may be formed either in a silicon substrate layer or the carbon doped silicon substrate.

Abstract: An advanced transistor with threshold voltage set dopant structure includes a gate with length Lg and a well doped to have a first concentration of a dopant. A screening region is positioned between the well and the gate and has a second concentration of dopant greater than 5×1018 dopant atoms per cm3. A threshold voltage set region is formed by placement of a threshold voltage offset plane positioned above the screening region. The threshold voltage set region may be formed by delta doping and have a thickness between Lg/5 and Lg/1. The structure uses minimal or no halo implants to maintain channel dopant concentration at less than 5×1017 dopant atoms per cm3.

Abstract: Methods for depositing a silicon-containing film are described. The methods may include delivering a silicon compound to a surface or a substrate, and reacting the silicon compound to grow the silicon-containing film. The silicon compound may be one or more compounds having a formula selected from the group Si4X8, Si4X10, Si5X10, and Si5X12, where X is independently a hydrogen or halogen.

Abstract: Embodiments of the invention relate to methods for depositing silicon-containing materials on a substrate. In one example, a method for selectively and epitaxially depositing a silicon-containing material is provided which includes positioning and heating a substrate containing a crystalline surface and a non-crystalline surface within a process chamber, exposing the substrate to a process gas containing neopentasilane, and depositing an epitaxial layer on the crystalline surface. In another example, a method for blanket depositing a silicon-containing material is provide which includes positioning and heating a substrate containing a crystalline surface and feature surfaces within a process chamber and exposing the substrate to a process gas containing neopentasilane and a carbon source to deposit a silicon carbide blanket layer across the crystalline surface and the feature surfaces.

Abstract: Embodiments of the invention generally provide a composition of silicon compounds and methods for using the silicon compounds to deposit a silicon-containing film. The processes employ introducing the silicon compound to a substrate surface and depositing a portion of the silicon compound, the silicon motif, as the silicon-containing film. The ligands are another portion of the silicon compound and are liberated as an in-situ etchant. The in-situ etchants supports the growth of selective silicon epitaxy. Silicon compounds include SiRX6, Si2RX6, Si2RX8, wherein X is independently hydrogen or halogen and R is carbon, silicon or germanium. Silicon compound also include compounds comprising three silicon atoms, fourth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen, as well as, comprising four silicon atoms, fifth atom of carbon, silicon or germanium and atoms of hydrogen or halogen with at least one halogen.

Abstract: Methods for depositing a silicon-containing film are described. The methods may include delivering a silicon compound to a surface or a substrate, and reacting the silicon compound to grow the silicon-containing film. The silicon compound may be one or more compounds having a formula selected from the group Si4X8, Si4X10, Si5X10, and Si5X12, where X is independently a hydrogen or halogen.

Abstract: Embodiments of the invention relate to methods for depositing silicon-containing materials on a substrate. In one example, a method for selectively and epitaxially depositing a silicon-containing material is provided which includes positioning and heating a substrate containing a crystalline surface and a non-crystalline surface within a process chamber, exposing the substrate to a process gas containing neopentasilane, and depositing an epitaxial layer on the crystalline surface. In another example, a method for blanket depositing a silicon-containing material is provide which includes positioning and heating a substrate containing a crystalline surface and feature surfaces within a process chamber and exposing the substrate to a process gas containing neopentasilane and a carbon source to deposit a silicon carbide blanket layer across the crystalline surface and the feature surfaces.

Abstract: A method implemented by one or more processors, including receiving first information relating a plurality of flow rates of a species to corresponding concentrations of the species within films generated using the flow rates; receiving a desired concentration profile of the species within a desired film; and generating a plurality of process steps that, when performed, would form the desired film with the desired concentration profile by controlling the flow rate of the species based, in part, on the first information and the desired concentration profile, wherein a first concentration of the species at a first point in the desired concentration profile differs from a second concentration of the species at a second point in the desired concentration profile. A computer-readable medium, system and apparatus are also disclosed.

Abstract: A method is provided wherein a temperature reading error of a pyrometer is avoided. An upper pyrometer is used to detect infrared radiation from a test layer formed on a test substrate under standard processing conditions. The infrared radiation from the test layer has a period having a length which is indicative of growth rate of the layer. The period is generally inversely proportional to the growth rate. The growth rate is directly related to the temperature.