Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: An embodiment of this application provides a method and apparatus for testing control software, and a computer-readable storage medium to reduce the time consumed in the simulation-based debugging and enhance efficiency. The method may include obtaining test information of a plurality of fault signals; and injecting, based on the test information of the plurality of fault signals, the plurality of fault signals into a simulation environment in sequence to obtain test results of the plurality of fault signals handled by the control software, where the simulation environment may be a simulation environment of a control object of the control software.

Abstract: A method for creating kinematic pair objects. Kinematic pairs are included in a first facility. The first facility is equipped with control software. The method includes obtaining a first file that includes names of N kinematic pairs, calling the control software to read the names of the N kinematic pairs in the first file, and calling the control software to create N kinematic pair objects. N is an integer greater than or equal to 1. The N kinematic pair objects are determined based on the names of the N kinematic pairs read by the control software. The names of the N kinematic pairs are in one-to-one correspondence to the N kinematic pair objects.

Abstract: Provided are a method for modifying parameters of kinematic pairs. The method includes: acquiring a first parameter modification command used for performing instruction to modify a value of a first pose of first kinematic pairs; determining a plurality of first devices in a plurality of devices according to the first parameter modification command, where, the plurality of devices are configured to have kinematic pair driver software, and the plurality of first devices are a plurality of devices including the first kinematic pairs; acquiring a second parameter modification command including a target value of the first pose of the first kinematic pairs; and invoking the kinematic pair driver software of the plurality of first devices according to the second parameter modification command so as to update the value of the first pose of the plurality of first kinematic pairs into the target value of the first pose.

Abstract: A display substrate and a display apparatus. The display substrate has a display region (AA) and an opening (O) located in the display region (AA). The opening (O) penetrates the display substrate, and the display substrate comprises a base substrate (BS), a driving circuit layer, a light-emitting device layer, an encapsulation layer and a touch layer (TL). The driving circuit layer is arranged on the base substrate (BS), and comprises a first signal line (L1) at least partially surrounding the opening (O). The light-emitting device layer is arranged on the side of the driving circuit layer distant from the base substrate (BS). The encapsulation layer is arranged on the side of the light-emitting device layer distant from the base substrate (BS).

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: A display panel and a display device are provided. The display panel includes a base substrate, a plurality of pixel drive circuit units, n first signal lines, a touch layer, and a light emitting element. A distance between first extending portions of two adjacent first signal lines is greater than a distance between first bending portions of the two adjacent first signal lines. An orthogonal projection overlap area between the first connecting portion and first extending portions of the n first signal lines is S1, and an orthogonal projection overlap area between the first connecting portion and first bending portions of the n first signal lines is S2. S1?S2. A length of a first extending portion of at least one first signal line is L1, a distance between the first extending portion of at least one first signal line and the second electrode is H1, and H1?(S1/n)/L1.

Abstract: A medium thickness detection device includes: a light emitting element; a constant-current control circuit controlling, in a constant-current manner, the light emitting element to output light passing through a medium for an irradiation time; a light-receiving element receiving the light passing through the medium to obtain an analog signal; a receiver circuit receiving the analog signal; a maximum holding circuit holding a maximum of the analog signal; an analog-to-digital converter circuit reading the maximum of the analog signal and converting the maximum of the analog signal into a digital signal; a reset circuit resetting the maximum holding circuit; and a processor controlling operations of the constant-current control circuit, the reset circuit and the analog-to-digital converter circuit, and determining a thickness of the medium according to the digital signal when a specification of the medium is unknown.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: A method of thinning a wafer includes measuring an initial thickness of the wafer. The method further includes calculating a polishing time using the initial thickness. The method further includes polishing the wafer for a first duration equal to the polishing time to obtain a polished wafer. The method further includes measuring a polished thickness of the polished wafer. The method further includes calculating an etching time using the polished thickness. The method further includes etching the polished wafer for a second duration equal to the etching time to obtain an etched wafer, wherein the wafer has a total thickness variation of less than or equal to 0.15 ?m after etching the polished wafer.

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Abstract: The present disclosure provides an integrated flywheel with shared cylinders and a manufacturing method therefor, comprising gear rings and support portions comprising a plurality of bridge portions with a spoke and a cylinder. Between adjacent bridge portions, the first spoke overlaps one end of a cylinder on a next-stage support portion to form a first overlap joint, one end of the first cylinder overlaps an inner side of the first spoke, and the other end of the first cylinder overlaps and is fixed with an outer side of the second spoke to form a second overlap joint. A first gear ring with a greater diameter is fixed at the first overlap joints, and a third gear ring with a less diameter is fixed at the second overlap joints. The integrated flywheel has advantages of low mass, good manufacturability and high production efficiency.

Abstract: An apparatus includes a first metrology tool configured to measure an initial thickness of a wafer. The apparatus includes a controller connected to the first metrology tool and configured to calculate a polishing time based on a material removal rate, a predetermined thickness and the initial thickness of the wafer. The apparatus includes a polishing tool connected to the controller and configured to polish the wafer for a first duration equal to the polishing time. The apparatus includes a second metrology tool connected to the controller and configured to measure a polished thickness. The controller is configured for receiving the initial thickness from the first metrology tool and the polished thickness from the second metrology tool, updating the material removal rate based on the predetermined thickness, the polishing time and the polished thickness, and calculating an etching time for etching the polished wafer using the polished thickness.

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Abstract: A magnetic levitation motor has a housing, a plurality of stators and a plurality of rotors. The housing has a shaft hole there through, the shaft hole accepting a bearing, the bearing rotatably engages with a rotating shaft that extends from two ends of the housing, and a plurality of fastening portions are disposed on the rotating shaft. A main body section is disposed between at least two of the fastening portions, and the housing having a plurality of dividers to define a plurality of containing spaces. The stator has a fixing disk wrapped with a coil and having a through aperture the fixing disk, and the fixing disk has a plurality of first magnets circularly and radially arranged. The rotor has a moving disk with a toothed hole at a center the moving disk, and the moving disk having a plurality of second magnets arranged circularly and radially.

Abstract: A polishing pad includes a pad layer and one or more polishing structures over an upper surface of the pad layer, where each of the one or more polishing structures has a pre-determined shape and is formed at a pre-determined location of the pad layer, where the one or more polishing structures comprise at least one continuous line shaped segment extending along the upper surface of the pad layer, where each of the one or more polishing structures is a homogeneous material.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A method and apparatus for determining the sealability of an oil & gas well sealant fluid, whereby a cylindrical cell assembly capable of withstanding high temperature and high pressure with an electromagnetic heater positioned radially outside the cell body while partly filled with the sealant fluid. A leakage assembly in connection to the cylindrical cell assembly allows the sealant fluid to continuously flow through a leakage element at a desired differential pressure, and the residual fluid is drained into said cell by a cycling pipeline system. The real-time pressure may be recorded and transmitted to a control system including data acquisition and control units so as to monitor and measure the sealability of fluid in the downhole leakage.

Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.