Patents by Inventor Lang WANG

Lang WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250007568
    Abstract: The present disclosure provides an intelligent reflection surface, a signal sending method and apparatus, and a storage medium, and belong to the field of wireless communication. In embodiments of this application, the intelligent reflection surface receives adjustment information sent by a first wireless device, and adjusts an on/off state of the intelligent reflection surface based on the adjustment information.
    Type: Application
    Filed: September 12, 2024
    Publication date: January 2, 2025
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yujian Tang, Jiachen Liu, Yu Su, Lang Wang, Jun Chen
  • Patent number: 12103101
    Abstract: To provide a vibration conversion apparatus capable of reducing occurrence of cracks although using a longitudinal vibration converter for obtaining a torsional vibration. The vibration conversion apparatus comprises: a first longitudinal vibration converter and a longitudinal-torsional transducer having a one-wavelength torsional vibrator portion and a first flexural resonator portion. The first flexural resonator portion is interposed between the first longitudinal vibration converter and the one-wavelength torsional vibrator portion. The first flexural resonator portion is configured such that when a longitudinal vibration generated by at least the first longitudinal vibration converter is received from one end of the first flexural resonator portion, the first flexural resonator portion is bent and imparts a rotational force from the other end of the first flexural resonator portion to the one-wavelength torsional vibrator portion.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 1, 2024
    Assignee: Branson Ultrasonics Corporation
    Inventors: Osamu Tamamoto, Lang Wang
  • Publication number: 20240313051
    Abstract: A semiconductor structure includes a substrate, a nanowire disposed over the substrate, a metal gate electrode layer and a gate dielectric layer. A dielectric layer is formed on the substrate. The nanowire has a first portion and a second portion. The nanowire has a first portion and a second portion, the first portion of the nanowire comprises a first semiconductor layer and a second semiconductor layer surrounded by the first semiconductor layer, the second portion comprises the second semiconductor layer. The metal gate electrode layer surrounds the first portion of the nanowire. The gate dielectric layer is disposed between the metal gate electrode layer and the nanowire.
    Type: Application
    Filed: May 27, 2024
    Publication date: September 19, 2024
    Inventors: TE-MING KUNG, YING-LANG WANG, KEI-WEI CHEN, WEN-HSI LEE, SHU WEI CHANG
  • Publication number: 20240302255
    Abstract: Disclosed are methods and compositions for use in preparing dynamic biological macromolecules for high-resolution cryo-electron microscopy or cryo-electron tomography imaging. The compositions contain a metallo-supramolecular branched polymer with a positive zeta potential, containing a hydrophilic polymer segment, a chelating chemical group, and a metal ion. The hydrophilic polymer segment is covalently bonded to the chelating chemical group that is in turn bonded to the metal ion via a dative bond. The methods and compositions can be used to improve particle distribution in vitreous ice and/or to change particle orientations in vitreous ice. Accordingly, the methods and compositions can be utilized to improve particle distribution for high resolution structure determination using single-particle cryo-EM.
    Type: Application
    Filed: June 8, 2022
    Publication date: September 12, 2024
    Inventors: Shangyu DANG, Yixin XU, Yufeng WANG, Lang WANG
  • Patent number: 12068195
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: June 7, 2023
    Date of Patent: August 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Publication number: 20240223428
    Abstract: This application provides a signal transmission method and an apparatus, to reduce an envelope ripple of a transmission signal. The method includes: A base station obtains a first bit sequence and maps the first bit sequence to a first modulation symbol sequence, where a value of each modulation symbol in the first modulation symbol sequence belongs to a first constellation point set, the first constellation point set includes K modulation symbols, and each of the K modulation symbols has a different amplitude. The base station sequentially performs a DFT, weighting, and an IFFT on each modulation symbol in the first modulation symbol sequence to obtain a first signal. Based on the foregoing solution, an envelope ripple of the signal generated by the base station in time domain is small. This facilitates demodulation of the transmission signal by a terminal.
    Type: Application
    Filed: March 14, 2024
    Publication date: July 4, 2024
    Inventors: Jun CHEN, Mao Yan, Yiling Wu, Sunjie Wang, Yujian Tang, Lang Wang
  • Patent number: 12021117
    Abstract: A method of forming a semiconductor structure includes following operations. A substrate including a silicon (Si) layer is received. An amorphous germanium (Ge) layer is formed on the Si layer. A barrier layer is formed over the amorphous Ge layer. The substrate is annealed to transform the Si layer and the Ge layer to form a single crystalline SiGe layer. A Ge concentration is in a positive correlation with a ratio of a thickness of the Ge layer and a thickness of the Si layer.
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: June 25, 2024
    Inventors: Te-Ming Kung, Ying-Lang Wang, Kei-Wei Chen, Wen-Hsi Lee, Shu Wei Chang
  • Patent number: 11955553
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Grant
    Filed: February 24, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Publication number: 20240088225
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
  • Publication number: 20240067476
    Abstract: A medium thickness detection device includes: a light emitting element; a constant-current control circuit controlling, in a constant-current manner, the light emitting element to output light passing through a medium for an irradiation time; a light-receiving element receiving the light passing through the medium to obtain an analog signal; a receiver circuit receiving the analog signal; a maximum holding circuit holding a maximum of the analog signal; an analog-to-digital converter circuit reading the maximum of the analog signal and converting the maximum of the analog signal into a digital signal; a reset circuit resetting the maximum holding circuit; and a processor controlling operations of the constant-current control circuit, the reset circuit and the analog-to-digital converter circuit, and determining a thickness of the medium according to the digital signal when a specification of the medium is unknown.
    Type: Application
    Filed: June 14, 2023
    Publication date: February 29, 2024
    Inventors: WEI CHIN CHENG, YU-LANG WANG
  • Patent number: 11855146
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
    Type: Grant
    Filed: January 17, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
  • Publication number: 20230360919
    Abstract: A method of thinning a wafer includes measuring an initial thickness of the wafer. The method further includes calculating a polishing time using the initial thickness. The method further includes polishing the wafer for a first duration equal to the polishing time to obtain a polished wafer. The method further includes measuring a polished thickness of the polished wafer. The method further includes calculating an etching time using the polished thickness. The method further includes etching the polished wafer for a second duration equal to the etching time to obtain an etched wafer, wherein the wafer has a total thickness variation of less than or equal to 0.15 ?m after etching the polished wafer.
    Type: Application
    Filed: July 21, 2023
    Publication date: November 9, 2023
    Inventors: Yuan-Hsuan CHEN, Kei-Wei CHEN, Ying-Lang WANG, Kuo-Hsiu WEI
  • Publication number: 20230317519
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Application
    Filed: June 7, 2023
    Publication date: October 5, 2023
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: 11745826
    Abstract: The present disclosure provides an integrated flywheel with shared cylinders and a manufacturing method therefor, comprising gear rings and support portions comprising a plurality of bridge portions with a spoke and a cylinder. Between adjacent bridge portions, the first spoke overlaps one end of a cylinder on a next-stage support portion to form a first overlap joint, one end of the first cylinder overlaps an inner side of the first spoke, and the other end of the first cylinder overlaps and is fixed with an outer side of the second spoke to form a second overlap joint. A first gear ring with a greater diameter is fixed at the first overlap joints, and a third gear ring with a less diameter is fixed at the second overlap joints. The integrated flywheel has advantages of low mass, good manufacturability and high production efficiency.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 5, 2023
    Assignee: HUNAN SROAD TECHNOLOGY CO., LTD.
    Inventors: Tao Xie, Xiaoran Zheng, Jizhou Ou, Hui Xue, Lang Wang, Yaoyao Huang
  • Patent number: 11728172
    Abstract: An apparatus includes a first metrology tool configured to measure an initial thickness of a wafer. The apparatus includes a controller connected to the first metrology tool and configured to calculate a polishing time based on a material removal rate, a predetermined thickness and the initial thickness of the wafer. The apparatus includes a polishing tool connected to the controller and configured to polish the wafer for a first duration equal to the polishing time. The apparatus includes a second metrology tool connected to the controller and configured to measure a polished thickness. The controller is configured for receiving the initial thickness from the first metrology tool and the polished thickness from the second metrology tool, updating the material removal rate based on the predetermined thickness, the polishing time and the polished thickness, and calculating an etching time for etching the polished wafer using the polished thickness.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hsuan Chen, Kei-Wei Chen, Ying-Lang Wang, Kuo-Hsiu Wei
  • Patent number: 11710659
    Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: July 25, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Li-Chieh Wu, Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Ying-Lang Wang, Su-Hao Liu, Kuo-Ju Chen, Liang-Yin Chen, Huicheng Chang, Ting-Kui Chang, Chia Hsuan Lee
  • Patent number: 11705795
    Abstract: A magnetic levitation motor has a housing, a plurality of stators and a plurality of rotors. The housing has a shaft hole there through, the shaft hole accepting a bearing, the bearing rotatably engages with a rotating shaft that extends from two ends of the housing, and a plurality of fastening portions are disposed on the rotating shaft. A main body section is disposed between at least two of the fastening portions, and the housing having a plurality of dividers to define a plurality of containing spaces. The stator has a fixing disk wrapped with a coil and having a through aperture the fixing disk, and the fixing disk has a plurality of first magnets circularly and radially arranged. The rotor has a moving disk with a toothed hole at a center the moving disk, and the moving disk having a plurality of second magnets arranged circularly and radially.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 18, 2023
    Inventor: Jin-Lang Wang
  • Patent number: 11685013
    Abstract: A polishing pad includes a pad layer and one or more polishing structures over an upper surface of the pad layer, where each of the one or more polishing structures has a pre-determined shape and is formed at a pre-determined location of the pad layer, where the one or more polishing structures comprise at least one continuous line shaped segment extending along the upper surface of the pad layer, where each of the one or more polishing structures is a homogeneous material.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20230197852
    Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.
    Type: Application
    Filed: February 24, 2023
    Publication date: June 22, 2023
    Inventors: Su-Hao Liu, Kuo-Ju Chen, Wen-Yen Chen, Ying-Lang Wang, Liang-Yin Chen, Li-Ting Wang, Huicheng Chang
  • Patent number: 11674887
    Abstract: A method and apparatus for determining the sealability of an oil & gas well sealant fluid, whereby a cylindrical cell assembly capable of withstanding high temperature and high pressure with an electromagnetic heater positioned radially outside the cell body while partly filled with the sealant fluid. A leakage assembly in connection to the cylindrical cell assembly allows the sealant fluid to continuously flow through a leakage element at a desired differential pressure, and the residual fluid is drained into said cell by a cycling pipeline system. The real-time pressure may be recorded and transmitted to a control system including data acquisition and control units so as to monitor and measure the sealability of fluid in the downhole leakage.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: June 13, 2023
    Assignees: ZHEJIANG OCEAN UNIVERSITY, YANGTZE UNIVERSITY
    Inventors: Lin Xu, Xiaohe Huang, Yue Huang, Mingbiao Xu, Yingying Guo, Huanzhi Feng, Xijin Xing, Li Xu, Lang Wang