Patents by Inventor Lang WANG

Lang WANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190152241
    Abstract: A paper tray includes a casing, a lifting mechanism, a weight detector, a storage unit, and a control unit. An accommodating space is formed inside the casing. The lifting mechanism is disposed inside the accommodating space for supporting and lifting at least one sheet of paper. The weight detector is disposed on the lifting mechanism for detecting a weight of the at least one sheet of paper. The storage unit is for storing paper information and a predetermined amount. The control unit is electrically connected to the weight detector and the storage unit. The control unit determines an amount of the at least one sheet of paper according to relation of the weight and the paper information and outputs a supplementary alert to an apparatus for reminding users when the control unit determines the amount of the at least one sheet of paper is less than the predetermined amount.
    Type: Application
    Filed: September 27, 2018
    Publication date: May 23, 2019
    Inventors: Ming-Chung Li, Yu-Lang Wang, Kuang-Huan Li, Xiang-Chi Lee
  • Patent number: 10283702
    Abstract: Methods for a resistive random access memory (RRAM) device are disclosed. A bottom electrode is formed over a substrate. A top electrode is formed over the bottom electrode. A resistive switching layer is formed interposed between the top electrode and the bottom electrode. The resistive switching is made of a composite of a metal, Si, and O, formed by oxidation of a metal silicide of a metal, co-deposition of the metal and silicon in oxygen ambiance, co-deposition of a metal oxide of the metal and silicon, or co-deposition of a metal oxide of the metal and silicon oxide. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
  • Patent number: 10276621
    Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Chieh Chang, Jian-Shin Tsai, Chih-Chang Huang, Ing-Ju Lee, Ching-Yao Sun, Jyun-Ru Wu, Ching-Che Huang, Szu-An Wu, Ying-Lang Wang
  • Patent number: 10253968
    Abstract: An operating button includes a light source, a push rod with a diverging lens, and an operating head with a condensing lens. The optical center of the diverging lens, the optical center of the condensing lens and the light source are in the same line such that light rays generated by the light source pass through the diverging lens and the converging lens before exiting the operating head as parallel light.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 9, 2019
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventors: Zhi Cheng, Jian Ming Liu, Song Liu, Radek Melich, Hua Lang Wang, Hong Yang, Shi Bo Yin
  • Publication number: 20180375024
    Abstract: The present disclosure relates to an RRAM device having an electrode with an oxygen barrier structure, which is configured to improve RRAM reliability by mitigating oxygen movement and thereby maintaining oxygen within close proximity of a dielectric data storage layer, and an associated method of formation. In some embodiments, the RRAM device has a bottom electrode disposed over a lower interconnect layer surrounded by a ILD layer. A dielectric data storage layer having a variable resistance is located above the bottom electrode, and a multi-layer top electrode disposed over the dielectric data storage layer. The multi-layer top electrode has conductive top electrode layers separated by an oxygen barrier structure configured to mitigate movement of oxygen within the multi-layer top electrode. By including an oxygen barrier structure within the top electrode, the reliability of the RRAM device is improved since oxygen is kept close to the dielectric data storage layer.
    Type: Application
    Filed: March 29, 2018
    Publication date: December 27, 2018
    Inventors: Wen-Ting Chu, Tong-Chern Ong, Ying-Lang Wang
  • Publication number: 20180371402
    Abstract: A medium composition for producing alpha-glucosidase inhibitors fermented from Paenibacillus, comprising chitin as a carbon source, proteome as a nitrogen source, and inorganic salts. Via a fermentation by Paenibacillus, it may be transferred into a medium residue having a large amount of alpha-glucosidase inhibitors. Therefore, the medium composition has the efficiency of inhibiting alpha-glucosidase.
    Type: Application
    Filed: February 27, 2018
    Publication date: December 27, 2018
    Inventors: SAN-LANG WANG, VAN-BON NGUYEN
  • Patent number: 10159668
    Abstract: A composition for inhibiting ?-glucosidase has lower side effects to a user, other than the inhibition of ?-glucosidase. The composition comprises adenine, (3-hydroxy-dl-proline, nicotinic acid, (3,6-dioxo-piperazin-2-yl)-acetic acid amide, 2-ethylhexyl heptanoate, and a pharmaceutically compatible salt.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 25, 2018
    Assignee: TAMKANG UNIVERSITY
    Inventors: San-Lang Wang, Van-Bon Nguyen
  • Publication number: 20180337113
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a gate structure separating source and drain (S/D) features. The semiconductor device further includes a first dielectric layer formed over the substrate, the first dielectric layer including a first interconnect structure in electrical contact with the S/D features. The semiconductor device further includes an intermediate layer formed over the first dielectric layer, the intermediate layer having a top surface that is substantially coplanar with a top surface of the first interconnect structure. The semiconductor device further includes a second dielectric layer formed over the intermediate layer, the second dielectric layer including a second interconnect structure in electrical contact with the first interconnect structure and a third interconnect structure in electrical contact with the gate structure.
    Type: Application
    Filed: July 27, 2018
    Publication date: November 22, 2018
    Inventors: Jeng Min Liang, Ying-Lang Wang, Kei-Wei Chen, Chi-Wen Liu, Kuo-Hsiu Wei, Kuo-Feng Huang
  • Publication number: 20180296552
    Abstract: A composition for inhibiting ?-glucosidase has lower side effects to a user, other than the inhibition of ?-glucosidase. The composition comprises adenine, (3-hydroxy-dl-proline, nicotinic acid, (3,6-dioxo-piperazin-2-yl)-acetic acid amide, 2-ethylhexyl heptanoate, and a pharmaceutically compatible salt.
    Type: Application
    Filed: February 12, 2018
    Publication date: October 18, 2018
    Inventors: SAN-LANG WANG, VAN-BON NGUYEN
  • Patent number: 10096672
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type region including a first conductivity type impurity. A first gate structure is on the semiconductor substrate overlying the first conductivity type region. A second conductivity type region including a second conductivity type impurity is formed in the semiconductor substrate. A barrier layer is located between the first conductivity type region and the second conductivity type region. The barrier layer prevents diffusion of the second conductivity type impurity from the second conductivity type region into the first conductivity type region.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Chih Chen, Chih-Mu Huang, Fu-Tsun Tsai, Meng-Yi Wu, Yung-Fa Lee, Ying-Lang Wang
  • Publication number: 20180281152
    Abstract: A slurry dispensing unit for a chemical mechanical polishing (CMP) apparatus is provided. The slurry dispensing unit includes a nozzle, a mixer, a first fluid source, and a second fluid source. The nozzle is configured to dispense a slurry. The mixer is disposed upstream of the nozzle. The first fluid source is connected to the mixer through a first pipe and configured to provide a first fluid including a first component of the slurry. The second fluid source is connected to the mixer through a second pipe and configured to provide a second fluid including a second component of the slurry, wherein the second component is different from the first component.
    Type: Application
    Filed: July 11, 2017
    Publication date: October 4, 2018
    Inventors: Kei-Wei CHEN, Chih-Hung CHEN, Ying-Lang WANG
  • Publication number: 20180269307
    Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.
    Type: Application
    Filed: January 19, 2018
    Publication date: September 20, 2018
    Inventors: Chih Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Patent number: 10058974
    Abstract: A method for performing a CMP process is provided. The method includes performing the CMP process. The method further includes during the CMP process detecting a motion of a carrier head about a rotation axis beside a polishing pad. The method also includes producing a control signal corresponding to a detected result of the motion. In addition, the method includes prohibiting the rotation of the carrier head about a rotation axis by a driving motor which is controlled by the control signal. And, the method includes selecting a point of time at which the CMP process is terminated after the control signal is substantially the same as a threshold value.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: August 28, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chih-Hung Chen, Kei-Wei Chen, Ying-Lang Wang
  • Publication number: 20180151667
    Abstract: A method includes forming a flowable dielectric layer in a trench of a substrate; curing the flowable dielectric layer; and annealing the cured flowable dielectric layer to form an insulation structure and a liner layer. The insulation structure is formed in the trench, the liner layer is formed between the insulation structure and the substrate, and the liner layer includes nitrogen.
    Type: Application
    Filed: January 8, 2018
    Publication date: May 31, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ming LIN, Shiu-Ko JANGJIAN, Chun-Che LIN, Ying-Lang WANG, Wei-Ken LIN, Chuan-Pu LIU
  • Patent number: 9967657
    Abstract: A directional loudspeaker box with directional acoustic transmission holes includes a hollow housing and a loudspeaker. The hollow housing is provided with a front opening at the front end and has a peripheral portion adjacent to the front opening and formed with a plurality of directional acoustic transmission holes. The loudspeaker is fixed in the hollow housing and generates sound that can propagate out of the hollow housing through the front opening and the directional acoustic transmission holes. The angle at which each directional acoustic transmission hole is formed with respect to the central axis of the loudspeaker is a function of the axial distance between the directional acoustic transmission hole and the loudspeaker, wherein the smaller the axial distance, the larger the angle, and the larger the axial distance, the smaller the angle. Thus, the directional loudspeaker box effectively deals with near- and far-field sound effects.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: May 8, 2018
    Assignee: LONGINESTENO TECHNOLOGY COMPLEX CORPORATION
    Inventor: Chao-Lang Wang
  • Patent number: 9960260
    Abstract: A Metal Oxide Thin Film Transistor (MOTFT) and a preparation method thereof are provided. The preparation method includes the following steps in turn: Step a: a metal conductive layer is prepared and patterned as a gate on a substrate; Step b: a first insulating thin film is deposited as a gate insulating layer on the metal conductive layer; Step c: a metal oxide thin film is deposited and patterned as an active layer on the gate insulating layer; Step d: an organic conductive thin film is deposited as a back channel etch protective layer on the active layer; Step e: a metal layer is deposited on the back channel etch protective layer and then patterned as pattern of a source electrode and a drain electrode; Step f: a second insulating thin film is deposited as a passivation layer on the source electrode and the drain electrode.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: May 1, 2018
    Assignee: Guang Zhou New Vision Opto-Electronic Technology Co., Ltd.
    Inventors: Miao Xu, Dongxiang Luo, Hongmeng Li, Jiawei Pang, Ying Guo, Lang Wang
  • Publication number: 20180108836
    Abstract: Methods for a resistive random access memory (RRAM) device are disclosed. A bottom electrode is formed over a substrate. A top electrode is formed over the bottom electrode. A resistive switching layer is formed interposed between the top electrode and the bottom electrode. The resistive switching is made of a composite of a metal, Si, and O, formed by oxidation of a metal silicide of a metal, co-deposition of the metal and silicon in oxygen ambiance, co-deposition of a metal oxide of the metal and silicon, or co-deposition of a metal oxide of the metal and silicon oxide. There may be an additional tunnel barrier layer between the top electrode and the bottom electrode. The top electrode and the bottom electrode may comprise multiple sub-layers.
    Type: Application
    Filed: December 18, 2017
    Publication date: April 19, 2018
    Inventors: Ting-Chang Chang, Yong-En Syu, Fu-Yen Jian, Shih-Chieh Chang, Ying-Lang Wang
  • Patent number: 9931726
    Abstract: A wafer edge trimming tool includes an abrasive tape and a holding module configured to hold the abrasive tape against portions of an edge of a rotating wafer during a wafer edge trimming process.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tang-Kuei Chang, Kuo-Hsiu Wei, Kei-Wei Chen, Huai-Tei Yang, Ying-Lang Wang
  • Publication number: 20180061987
    Abstract: A method of fabricating a semiconductor device includes following steps. A trench is formed in a substrate. A barrier layer and an epitaxy layer are formed in sequence in the trench. The barrier layer has a first dopant. A source/drain recess cavity is formed by etching at least the epitaxial layer. A source/drain region is formed in the source/drain recess cavity. The source/drain region has a second dopant.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: I-Chih CHEN, Ying-Lang WANG, Chih-Mu HUANG, Ying-Hao CHEN, Wen-Chang KUO, Jung-Chi JENG
  • Patent number: 9871100
    Abstract: A trench structure of a semiconductor device includes a substrate, an isolation structure, and a liner layer. The substrate has a trench therein. The isolation structure is disposed in the trench. The liner layer is disposed between the substrate and the isolation structure. The liner layer includes nitrogen, and the liner layer has spatially various nitrogen concentration.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: January 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ming Lin, Shiu-Ko Jangjian, Chun-Che Lin, Ying-Lang Wang, Wei-Ken Lin, Chuan-Pu Liu