Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.

Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.

Abstract: A magnetic levitation motor has a housing, a plurality of stators and a plurality of rotors. The housing has a shaft hole there through, the shaft hole accepting a bearing, the bearing rotatably engages with a rotating shaft that extends from two ends of the housing, and a plurality of fastening portions are disposed on the rotating shaft. A main body section is disposed between at least two of the fastening portions, and the housing having a plurality of dividers to define a plurality of containing spaces. The stator has a fixing disk wrapped with a coil and having a through aperture the fixing disk, and the fixing disk has a plurality of first magnets circularly and radially arranged. The rotor has a moving disk with a toothed hole at a center the moving disk, and the moving disk having a plurality of second magnets arranged circularly and radially.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A method and apparatus for determining the sealability of an oil & gas well sealant fluid, whereby a cylindrical cell assembly capable of withstanding high temperature and high pressure with an electromagnetic heater positioned radially outside the cell body while partly filled with said sealant fluid. A minor-leak assembly in connection to said cylindrical cell assembly allows said sealant fluid to continuously flow through a leak sample at a desired differential pressure, and the residual fluid is drained into said cell by a cycling pipeline system. The real-time pressure may be recorded to transmitted to a control system comprised of data acquisition and control units so as to monitor and measure the sealability of fluid in the downhole minor leaks.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a resistive random access memory (RRAM) device. The method includes forming one or more bottom electrode films over a lower interconnect layer within a lower inter-level dielectric layer. A data storage film having a variable resistance is formed above the one or more bottom electrode films. A lower top electrode film including a metal is over the data storage film, one or more oxygen barrier films are over the lower top electrode film, and an upper top electrode film including a metal nitride is formed over the one or more oxygen barrier films. The one or more oxygen barrier films include one or more of a metal oxide film and a metal oxynitride film. The upper top electrode film is formed to be completely confined over a top surface of the one or more oxygen barrier films.

Abstract: This application discloses example radio frequency identification systems and example methods for constructing a relay network, a reader, and a repeater. One example radio frequency identification system includes a reader, a repeater, and a target tag. The reader can be configured to send a first signal to the repeater. The repeater can be configured to send an excitation signal to the target tag based on the first signal. The target tag can be configured to send a target backscatter signal based on excitation of the excitation signal, where the target backscatter signal carries electronic product code information. The reader can be further configured to receive the target backscatter signal and obtain the electronic product code information in the target backscatter signal.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Abstract: To provide a vibration conversion apparatus capable of reducing occurrence of cracks although using a longitudinal vibration converter for obtaining a torsional vibration. The vibration conversion apparatus comprises: a first longitudinal vibration converter and a longitudinal-torsional transducer having a one-wavelength torsional vibrator portion and a first flexural resonator portion. The first flexural resonator portion is interposed between the first longitudinal vibration converter and the one-wavelength torsional vibrator portion. The first flexural resonator portion is configured such that when a longitudinal vibration generated by at least the first longitudinal vibration converter is received from one end of the first flexural resonator portion, the first flexural resonator portion is bent and imparts a rotational force from the other end of the first flexural resonator portion to the one-wavelength torsional vibrator portion.

Abstract: Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) device. The RRAM device includes a bottom electrode that is disposed over a lower interconnect layer surrounded by a lower inter-level dielectric (ILD) layer. A data storage structure is arranged over the bottom electrode and a multi-layer top electrode is disposed over the data storage structure. The multi-layer top electrode includes conductive top electrode layers separated by an oxygen barrier structure that is configured to mitigate movement of oxygen between the conductive top electrode layers. A sidewall spacer is disposed directly over the bottom electrode and has a sidewall that covers outermost sidewalls of the conductive top electrode layers and the oxygen barrier structure.

Abstract: A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.

Abstract: A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer.

Abstract: A bonding pad structure comprises an interconnect layer, an isolation layer over the interconnect layer, a conductive pad, and one or more non-conducting stress-releasing structures. The conductive pad comprises a planar portion over the isolation layer, and one or more bridging portions extending through at least the isolation layer and to the interconnect layer for establishing electric contact therewith, wherein there is a trench in the one or more bridging portions. The one or more non-conducting stress-releasing structures are disposed between the isolation layer and the conductive pad. The trench is surrounded by one of the one or more non-conducting stress-releasing structures from a top view.