Patents by Inventor Lawrence A. Clevenger

Lawrence A. Clevenger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • TOP VIA PROCESS WITH DAMASCENE METAL
    Publication number: 20230094757
    Abstract: An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 30, 2023
    Inventors: Lawrence A. Clevenger, Brent Anderson, Nicholas Anthony Lanzillo, Christopher J. Penny, Kisik Choi, Robert ROBISON
  • Subtractive Skip-Level Power via Adjacent Recessed Damascene Signal Lines
    Publication number: 20230098433
    Abstract: An interconnect stack structure includes a first metal level of horizontal power line wiring; a second metal level of horizontal power line wiring; wherein the first metal level is not adjacent to the second metal level; two top-via structures comprising a first via and a second via, the two top-via structures being formed above the first metal level; wherein the first via has a first height and the second via has a second height, the first height being different from the second height; wherein the first via extends to connect the first metal level to the second metal level; wherein the second via extends to connect to the first metal level but not the second metal level; damascene intermediate metal lines between the first metal level and the second metal level; and damascene signal lines above the first via and the damascene intermediate metal lines.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Nicholas Anthony Lanzillo, Huai Huang, Hosadurga Shobha, Lawrence A. Clevenger
  • NANOSHEET TRANSISTORS WITH BURIED POWER RAILS
    Publication number: 20230094466
    Abstract: A semiconductor structure includes a substrate and a first field effect transistor (FET) formed on the substrate; the first FET includes a first FET first source-drain region, a first FET second source-drain region, a first FET gate between the first and second source-drain regions, and a first FET channel region adjacent the first FET gate and between the first FET first and second source-drain regions. Also included is a buried power rail, buried in the substrate, having a top at a level lower than the first FET channel region, and having buried power rail sidewalls. A first FET shared contact is electrically interconnected with the buried power rail and the first FET second source-drain region, and a first FET electrically isolating region is adjacent the buried power rail sidewalls and separates the buried power rail from the substrate.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Julien Frougier, Nicolas Loubet, Sagarika Mukesh, PRASAD BHOSALE, Ruilong Xie, Andrew Herbert Simon, Takeshi Nogami, Lawrence A. Clevenger, Roy R. Yu, Andrew M. Greene, Daniel Charles Edelstein
  • INSULATED PHASE CHANGE MEMORY USING POROUS DIELECTRICS
    Publication number: 20230093026
    Abstract: Insulated phase change memory devices are provided that include a first electrode; a second electrode; a phase change material disposed in an electrical path between the first electrode and the second electrode; and a porous dielectric configured to concentrate heat produced by a reset current carried through the phase change material between the first electrode and the second electrode to mitigate an amount of heat that escapes from the phase change material. The porous dielectric may be an inherently porous dielectric material or a dielectric material in which porous structures are induced during fabrication. Methods of fabrication of such devices are also provided.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Timothy Mathew PHILIP, Anirban CHANDRA, Kevin W. BREW, Lawrence A. CLEVENGER
  • SEMICONDUCTOR STRUCTURES WITH BACKSIDE GATE CONTACTS
    Publication number: 20230086033
    Abstract: A semiconductor structure comprises a substrate having a first side and a second side opposite the first side, and a gate for at least one transistor device disposed above the first side of the substrate. The structure may further include a buried power rail at least partially disposed in the substrate and a gate tie-down contact connecting the gate to the buried power rail from the second side of the substrate. The structure may further or alternatively include one or more source/drain regions disposed over the first side of the substrate, and a gate contact connecting to a portion of the gate from the second side of the substrate, the portion of the gate being adjacent to at least one of the one or more source/drain regions.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Lawrence A. Clevenger, Nicolas Loubet, Dechao Guo, Kisik Choi, Kangguo Cheng, Carl Radens
  • CIRCUIT DESIGN WATERMARKING
    Publication number: 20230090521
    Abstract: Methods and systems for watermarking a circuit design include defining a watermarked cell library that includes cells, each of which defines a design structure that corresponds to a manufacturable physical structure, at least one of which being a watermarked call that includes a watermark. The watermark is encoded using a design structure that extends beyond a respective cell boundary. A first circuit design file is generated for a device to be manufactured. The first circuit design file including at least one watermarked cell. The first circuit design file is sent to a manufacturer for fabrication of a corresponding device that includes a watermark structure that encodes an identifier.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Carl Radens, Lawrence A. Clevenger, Daniel James Dechene, Hsueh-Chung Chen
  • Integrated non volatile memory electrode thin film resistor cap and etch stop
    Patent number: 11610941
    Abstract: A non-volatile memory cell includes a thin film resistor (TFR) in series and between a top state influencing electrode and a top wire. The TFR limits or generally reduces the electrical current at the top state influencing electrode from the top wire. As such, non-volatile memory cell endurance may be improved and adverse impacts to component(s) that neighbor the non-volatile memory cell may be limited. The TFR is additionally utilized as an etch stop when forming a top wire trench associated with the fabrication of the top wire. In some non-volatile memory cells where cell symmetry is desired, an additional TFR may be formed between a bottom wire and a bottom state influencing electrode.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 21, 2023
    Assignee: International Business Machines Corporation
    Inventors: Kevin W. Brew, Takashi Ando, Michael Rizzolo, Lawrence A. Clevenger
  • Top via stack
    Patent number: 11600565
    Abstract: A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line, each disposed in a first dielectric layer and extending from the first etch stop layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer comprising a second dielectric layer disposed on a top surface of the first metallization layer and a first via and a second via in the second dielectric layer. The semiconductor structure further includes a first conductive material disposed on a top surface of the first conductive line in the first via. The semiconductor structure further includes a second conductive material disposed on a top surface of the second conductive line in the second via.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: March 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Lawrence A. Clevenger, Christopher J. Penny, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
  • TOP VIA PATTERNING USING METAL AS HARD MASK AND VIA CONDUCTOR
    Publication number: 20230067493
    Abstract: A semiconductor structure comprising a substrate, a first metal layer on top of the substrate, a second metal layer on top of the first metal layer and a dielectric layer adjacent to the second metal layer and at least part of the first metal layer and on top of at least part of the first metal layer. The first metal layer includes a via. The width of the second metal layer is the same as the width of the via of the first metal layer.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: Nicholas Anthony Lanzillo, Huai Huang, Hosadurga Shobha, Lawrence A. Clevenger, Chanro Park
  • ADVANCED METAL INTERCONNECTS WITH A REPLACEMENT METAL
    Publication number: 20230066614
    Abstract: An approach to provide a semiconductor structure using different two metal materials for interconnects in the middle of the line and the back end of the line metal layers of a semiconductor chip. The semiconductor structure includes the first metal material connecting both horizontally and vertically with the second metal material and the second metal material connecting both horizontally and vertically with the first metal material where the second metal material is more resistant to electromigration than the first metal material.
    Type: Application
    Filed: August 26, 2021
    Publication date: March 2, 2023
    Inventors: Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Brent Anderson
  • Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers
    Patent number: 11574875
    Abstract: A multi-chip package structure includes a chip interconnect bridge, a fan-out redistribution layer structure, a first integrated circuit chip, and a second integrated circuit chip. The chip interconnect bridge includes contact pads disposed on a top side of the chip interconnect bridge. The fan-out redistribution layer structure is disposed around sidewalls of the chip interconnect bridge and over the top side of the chip interconnect bridge. The first and second integrated circuit chips are direct chip attached to an upper surface of the fan-out redistribution layer structure, wherein the fan-out redistribution layer structure includes input/output connections between the contact pads on the top side of the chip interconnect bridge and the first and second integrated circuit chips.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: February 7, 2023
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Steven Lorenz Wright, Lawrence A. Clevenger
  • Authentication of medication delivery vehicle to facilitate medication release
    Patent number: 11574735
    Abstract: A delivery device includes a circuit for receiving an authentication signal. The delivery device contains a substance encapsulated therein. The delivery device determines whether a user is authenticated based upon the authentication signal and an identifier stored within the delivery device. The delivery device heats, responsive to determining that the user is not authenticated within a predetermined time period after the delivery device being ingested by the user, the substance encapsulated within the delivery device.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: February 7, 2023
    Assignee: Kyndryl, Inc.
    Inventors: Ira L. Allen, Gregory J. Boss, Lawrence A. Clevenger, Andrew R. Jones, Kevin C. McConnell, John E. Moore, Jr.
  • Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
    Patent number: 11574864
    Abstract: A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: February 7, 2023
    Assignee: Tessera LLC
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • TOP VIA CUT FILL PROCESS FOR LINE EXTENSION REDUCTION
    Publication number: 20230024306
    Abstract: An interconnect structure including a top via with a minimum line end extension comprises a cut filled with an etch stop material. The interconnect structure further comprises a line formed adjacent to the etch stop material. The interconnect structure further comprises a top via formed on the line adjacent to the etch stop material, wherein the top via utilizes the etch stop material to achieve minimum line extension.
    Type: Application
    Filed: July 23, 2021
    Publication date: January 26, 2023
    Inventors: Christopher J. Penny, Brent Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert ROBISON
  • SELF-ALIGNING SPACER TIGHT PITCH VIA
    Publication number: 20230016977
    Abstract: Embodiments disclosed herein describe semiconductor devices that include semiconductor structures and methods of forming the semiconductor structures. The semiconductor structures may include an upper conductive line, a first lower conductive line laterally insulated by a first lower dielectric region and a second lower dielectric region. The semiconductor structure also includes a lower level via region above the first lower conductive line. The lower level via region includes a dielectric blocking material and a spacer material.
    Type: Application
    Filed: July 19, 2021
    Publication date: January 19, 2023
    Inventors: Lawrence A. Clevenger, Brent Anderson, Nicholas Anthony Lanzillo
  • TOPVIA INTERCONNECT WITH ENLARGED VIA TOP
    Publication number: 20220415790
    Abstract: A top via interconnect with enlarged via top and a fabrication method therefor. One embodiment may comprise a semiconductor interconnect structure, comprising a first dielectric layer having a top surface, a bottom metal line formed in the dielectric layer, a second dielectric layer deposited above the top surface of the first dielectric layer, a via etched through the second dielectric layer above the bottom metal line, wherein the via exposes at least a portion of the top surface of the first dielectric layer, and a metal stud in the via that extends over the exposed at least a portion of the first dielectric layer. The metal stud in the via may further comprise a shoulder surface and a convex top surface.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Lawrence A. Clevenger, Chen Zhang, Brent Anderson, Nicholas Anthony Lanzillo
  • Stacked transistors with different channel widths
    Patent number: 11538720
    Abstract: A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: December 27, 2022
    Assignee: TESSERA LLC
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthiharan, John Zhang
  • FORMING SELF-ALIGNED VIAS AND AIR-GAPS IN SEMICONDUCTOR FABRICATION
    Publication number: 20220406658
    Abstract: A semiconductor device includes a first trench on a mandrel line through a top mask layer and stopping at a middle mask layer; and a second trench on a non-mandrel line through the top mask layer and stopping at the middle mask layer. A spacer material is removed from a structure resulting from etching the first trench and the second trench. The device includes a first via structure, formed using a removable material, in the first trench; a second via structure, formed using a removable material, in the second trench; an air-gap formed in a third trench created at a location of the spacer; a fourth trench formed by etching, to remove the first via structure and a first portion of a bottom mask layer under the first via structure; and a self-aligned line-end via on the mandrel line formed by filling the fourth trench with a conductive metal.
    Type: Application
    Filed: June 6, 2022
    Publication date: December 22, 2022
    Inventors: Lawrence A. Clevenger, Carl J. Radens, John H. Zhang
  • PHASE CHANGE MEMORY CELL GALVANIC CORROSION PREVENTION
    Publication number: 20220407005
    Abstract: A method for forming a phase-change memory cell includes depositing a metal layer over a wafer such that the metal layer covers connection structures of the wafer. The method further includes removing a portion of the metal layer such that the connection structures of the wafer remain covered by a remaining portion of the metal layer. The method further includes forming a phase-change memory stack on a stack area of the remaining portion of the metal layer. The method further includes removing the remaining portion of the metal layer except in the stack area.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 22, 2022
    Inventors: Injo Ok, Nicole Saulnier, Kevin W. Brew, Steven Michael McDermott, Lawrence A. Clevenger, Hari Prasad Amanapu, ADRA CARR, PRASAD BHOSALE
  • BACKSIDE FLOATING METAL FOR INCREASED CAPACITANCE
    Publication number: 20220406717
    Abstract: A semiconductor structure with one or more backside metal layers that include a plurality of portions of a floating metal layer separated by dielectric material from one or more power and ground lines in the backside metal layer. The height of each of the plurality of portions of the floating metal layer in each of the one or more backside metal layers and the distance between adjacent portions of the plurality of portions of the floating metal layer in each of the one or more backside metal layer correlates to the capacitance of each of the one or more backside metal layers.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 22, 2022
    Inventors: Nicholas Anthony Lanzillo, Hosadurga Shobha, Huai Huang, Lawrence A. Clevenger