Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: The present invention provides a method of making pure white light source. A phosphor powder which at least comprises three elements Zn, Se, and O is used for being excited by a purple-LED to emit pure red light (650 nm). The phosphor powder is coated on the purple-LED (Ex. chromaticity coordinate of x:0.26, y:0.10), and then placed aside a pure green-LED (or chip), when the purple-LED and the green-LED are electrified, a pure white light source with high color rendering index and high color saturation is obtained.

Abstract: Innovative structures and methods to store information capable of being represented by an n-bit binary word in electrically erasable Programmable Read-Only memories (EEPROM) are disclosed. To program a state below the highest threshold voltage for an N-type Field Effect Transistor (NFET) based EEPROM, the stored charge in the floating gate for the highest threshold voltage is erased down to the desired threshold voltage level of the EEPROM by applying an appropriate voltage to the control gate and drain of the NFET. The erase-down uses drain-avalanche-hot hole injection (DAHHI) for the NFET memory device to achieve the precise threshold voltage desired for the NFET EEPROM device. The method takes advantage of the self-convergent mechanism from the DAHHI current in the device, when the device reaches a steady state. For a “READ” operation, a read voltage is applied to the control gate and the drain is connected by a current load to the positive voltage supply.

Abstract: Non-differential sense amplifier circuitry for reading out Non-Volatile Memories (NVMs) and its operating methods are disclosed. Such non-differential amplifier circuitry requires exceptionally low power and achieves moderate sensing speed, as compared to a conventional sensing scheme.

Abstract: A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array.

Abstract: Dual Conducting Floating Spacer Metal Oxide Semiconductor Field Effect Transistors (DCFS MOSFETs) and methods for fabricate them using a process that is compatible with forming conventional MOSFETs are disclosed. A DCFS MOSFET can provide multi-bit storage in a single Non-Volatile Memory (NVM) memory cell. Like a typical MOSFET, a DCFS MOSFET includes a control gate electrode on top of a gate dielectric-silicon substrate, thereby forming a main channel of the device. Two electrically isolated conductor spacers are provided on both sides of the control gate and partially overlap two source/drain diffusion areas, which are doped to an opposite type to the conductivity type of the substrate semiconductor. The DCFS MOSFET becomes conducting when a voltage that exceeds a threshold is applied at the control gate and is coupled through the corresponding conducting floating spacer to generate an electrical field strong enough to invert the carriers near the source junction.

Abstract: Non-differential sense amplifier circuitry for reading out Non-Volatile Memories (NVMs) and its operating methods are disclosed. Such non-differential amplifier circuitry requires exceptionally low power and achieves moderate sensing speed, as compared to a conventional sensing scheme.

Abstract: A purchase-transaction-settled online consumer referral and reward system and method using real-time specific merchant sales information is provided for the advertising publishing industry. The system provides a pay per transaction platform that allows advertising publishers to monetize online and offline print media advertising by tracking and linking ad acceptance events to consummated consumer purchases and reward loyalty of consumers with subscription credits.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array.

Abstract: A motor-gearbox assembly includes a housing, a motor, and a gearbox. The housing includes a first alignment mechanism and a second alignment mechanism. The first alignment mechanism is at a first end of the housing and the second alignment mechanism is at a second end of the housing. The motor is mechanically positioned within the housing in accordance with the first alignment mechanism. The gearbox is mechanically positioned within the housing in accordance with the second alignment mechanisms to mechanically couple to the motor.

Abstract: A Non-Volatile Memory (NVM) cell in an NVM array is read out using other NVM cells in the array as a load element. Conventional load elements such as MOS transistors or resistors used to vary the bitline potential for the NVM cell readout in conventional NVM arrays are replaced with NVM cell(s) in the array. The omission of the extra MOS transistors or resistors for the load elements not only saves silicon area but also simplifies the bitline sensing circuitry design in the NVM array.

Abstract: An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Abstract: Features extracted from network browser pages and/or network search queries are leveraged to facilitate in detecting a user's browsing and/or searching intent. Machine learning classifiers constructed from these features automatically detect a user's online commercial intention (OCI). A user's intention can be commercial or non-commercial, with commercial intentions being informational or transactional. In one instance, an OCI ranking mechanism is employed with a search engine to facilitate in providing search results that are ranked according to a user's intention. This also provides a means to match purchasing advertisements with potential customers who are more than likely ready to make a purchase (transactional stage). Additionally, informational advertisements can be matched to users who are researching a potential purchase (informational stage).

Abstract: A method of forming a snack food product comprising partially scrambling eggs to obtain partially scrambled eggs having a curd size of about 1 to about 8 mm, mixing at least one food grade binder with the partially scrambled eggs, fully cooking the scrambled eggs, shaping the fully-cooked scrambled eggs, and battering the shaped scrambled eggs.

Abstract: A method programs a memory cell by controlling a reverse bias voltage across the PN junction between a source electrode of a MOSFET in the memory cell and the substrate, and pulling back the pinch-off point of the inversion region toward the source electrode, thereby increasing the programming efficiency of the memory cell. The method applies the main positive supply voltage Vcc to, the drain electrode of the memory cell from the chip main voltage supply, rather than the conventional method of using a higher voltage than Vcc. To optimize the programming condition, the source voltage and the substrate voltage are adjusted to achieve the maximum threshold voltage shifts under the same applied gate voltage pulse condition (i.e. using the gate pulse with the same voltage amplitude and duration regardless of the source voltage and the substrate voltage).

Abstract: Innovative self-adaptive and self-calibrated methods and structures for Multi-Level Cell (MLC) Non-Volatile Memory (NVM) are disclosed. In the MLC NVM, NVM cells are self-adaptively programmed into a fixed response tolerance window centered at the reference current or voltage corresponding to a selected level gate voltage applied to the controlled gates of NVM cells. The fixed response tolerance window is related to the threshold voltage tolerance window through the sense circuit gain. Properly choosing the sense circuit gain and the response window can control the threshold voltage tolerance window to a desired value. An incremental gate voltage larger than the threshold voltage tolerance window of each NVM cell will guarantee that each NVM cell will produce the correct output current (voltage) in response to applying to the control gate of the NVM cell the stepped voltage corresponding to the level of information stored in the NVM cell.

Abstract: A method and system to generate variants, including misspells from query log context usage are provided. Usage context obtained from the query logs is utilized to facilitate similarity determination. A Similarity Graph generation process generates a Similarity Graph, which is transformed to provide variants having varying edit distances. The transformed Similarity Graph is loaded into a hash table and provides query corrections in a search engine or related terms when bidding on keyword in an advertising system.

Abstract: Techniques for cross-selling keywords among keyword bidding entities (e.g., advertisers) based upon bidding patterns are provided. Utilizing a keyword suggestion tool in accordance with one embodiment, upon receipt of a first keyword, may examine all additional keywords that have been paired with the first keyword in the bidding patterns of other bidding entities and recommend one or more of the paired keywords to the bidding entity for consideration. In another embodiment, a keyword suggestion tool, upon receipt of a keyword from a first bidding entity, may examine the bidding pattern of the first bidding entity in comparison to the bidding patterns of other bidding entities to identify bidding entities that are similar to the bidding entity. Recommendations may then be made to the first bidding entity based upon keywords that the identified similar bidding entities have bid.

Abstract: A method and system are provided for forecasting keyword search volume. Keywords are categorized by concept and by the amount of data available for use in predicting future behavior. The keywords and/or the categories can also be categorized as seasonal or non-seasonal. A category level seasonal variation pattern can then be calculated based on keywords in the category that have sufficient historical data. A search volume can then be predicted for one or more keywords, with an appropriate calculation algorithm being selected based on the concept category, seasonal classification, and historical data available for the keywords.