Patents by Inventor Leonard Forbes

Leonard Forbes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • NROM flash memory devices on ultrathin silicon
    Patent number: 8183625
    Abstract: An NROM flash memory cell is implemented in an ultra-thin silicon-on-insulator structure. In a planar device, the channel between the source/drain areas is normally fully depleted. An oxide layer provides an insulation layer between the source/drain areas and the gate insulator layer on top. A control gate is formed on top of the gate insulator layer. In a vertical device, an oxide pillar extends from the substrate with a source/drain area on either side of the pillar side. Epitaxial regrowth is used to form ultra-thin silicon body regions along the sidewalls of the oxide pillar. Second source/drain areas are formed on top of this structure. The gate insulator and control gate are formed on top.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: May 22, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • LOCALIZED COMPRESSIVE STRAINED SEMICONDUCTOR
    Publication number: 20120122287
    Abstract: One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein.
    Type: Application
    Filed: January 24, 2012
    Publication date: May 17, 2012
    Inventor: Leonard Forbes
  • DRAM WITH NANOFIN TRANSISTORS
    Publication number: 20120119279
    Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.
    Type: Application
    Filed: January 24, 2012
    Publication date: May 17, 2012
    Inventor: Leonard Forbes
  • Low-temperature grown high quality ultra-thin CoTiOgate dielectrics
    Patent number: 8178413
    Abstract: A gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from alloys such as cobalt-titanium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which inhibits unwanted species migration and unwanted reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: May 15, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Reduction of random telegraph signal (RTS) and 1/f noise in silicon MOS devices, circuits, and sensors
    Publication number: 20120112251
    Abstract: The effects of random telegraph noise signal (RTS) or equivalently l/f noise on MOS devices, circuits, and sensors is described. Techniques are disclosed for minimizing this RTS and low frequency noise by minimizing the number of ionized impurity atoms in the wafer, substrate, well, pillar, or fin behind the channel of the MOS transistors. This noise reduction serves to reduce the errors in devices, sensors, and analog integrated circuits and error rates in digital integrated circuits and memories.
    Type: Application
    Filed: October 20, 2011
    Publication date: May 10, 2012
    Inventors: Leonard Forbes, Drake A. Miller
  • Fully depleted silicon-on-insulator CMOS logic
    Patent number: 8174081
    Abstract: A extractor implanted region is used in a silicon-on-insulator CMOS memory device. The extractor region is reversed biased to remove minority carriers from the body region of partially depleted memory cells. This causes the body region to be fully depleted without the adverse floating body effects.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: May 8, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • ELECTRONIC APPARATUS CONTAINING LANTHANIDE YTTRIUM ALUMINUM OXIDE
    Publication number: 20120108052
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by a monolayer or partial monolayer sequencing process such as using atomic layer deposition.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 3, 2012
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Tantalum silicon oxynitride high-K dielectrics and metal gates
    Patent number: 8168502
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.
    Type: Grant
    Filed: August 12, 2010
    Date of Patent: May 1, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC
    Publication number: 20120094477
    Abstract: Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.
    Type: Application
    Filed: December 20, 2011
    Publication date: April 19, 2012
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • METHODS OF FORMING TITANIUM SILICON OXIDE
    Publication number: 20120088373
    Abstract: A dielectric containing a titanium silicon oxide film and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments may include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments may include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures.
    Type: Application
    Filed: December 12, 2011
    Publication date: April 12, 2012
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Titanium aluminum oxide films
    Patent number: 8154066
    Abstract: A dielectric layer containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric layer produce a reliable dielectric layer for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a titanium aluminum oxide film.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: April 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • CHARGE TRAPPING DIELECTRIC STRUCTURES
    Publication number: 20120080740
    Abstract: A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.
    Type: Application
    Filed: December 12, 2011
    Publication date: April 5, 2012
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Backside nanoscale texturing to improve IR response of silicon solar cells and photodetectors
    Publication number: 20120080676
    Abstract: The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy.
    Type: Application
    Filed: November 3, 2011
    Publication date: April 5, 2012
    Inventor: Leonard Forbes
  • APPARATUS CONTAINING COBALT TITANIUM OXIDE
    Publication number: 20120074487
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition.
    Type: Application
    Filed: December 5, 2011
    Publication date: March 29, 2012
    Inventors: Kie Y. Ahn, Leonard Forbes
  • METHOD OF FORMING LUTETIUM AND LANTHANUM DIELECTRIC STRUCTURES
    Publication number: 20120074480
    Abstract: Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control.
    Type: Application
    Filed: December 2, 2011
    Publication date: March 29, 2012
    Inventors: Kie Y. Ahn, Leonard Forbes
  • CONDUCTIVE LAYERS FOR HAFNIUM SILICON OXYNITRIDE
    Publication number: 20120068272
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.
    Type: Application
    Filed: November 28, 2011
    Publication date: March 22, 2012
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Nanowire transistor with surrounding gate
    Patent number: 8134197
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Grant
    Filed: August 15, 2008
    Date of Patent: March 13, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Localized compressive strained semiconductor
    Patent number: 8124977
    Abstract: One aspect of the present subject matter relates to a method for forming strained semiconductor film. According to an embodiment of the method, a crystalline semiconductor bridge is formed over a substrate. The bridge has a first portion bonded to the substrate, a second portion bonded to the substrate, and a middle portion between the first and second portions separated from the substrate. The middle portion of the bridge is bonded to the substrate to provide a compressed crystalline semiconductor layer on the substrate. Other aspects are provided herein.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Nanolaminates of hafnium oxide and zirconium oxide
    Patent number: 8125038
    Abstract: A dielectric film containing a HfO2/ZrO2 nanolaminate and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. A dielectric layer containing a HfO2/ZrO2 nanolaminate may be realized in a wide variety of electronic devices and systems.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • DRAM with nanofin transistors
    Patent number: 8119484
    Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes