Patents by Inventor Leonard Forbes

Leonard Forbes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8120027
    Abstract: The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: February 21, 2012
    Inventor: Leonard Forbes
  • Patent number: 8119514
    Abstract: Methods of forming cobalt-doped indium-tin oxide structures are shown. Properties of structures include transparency, conductivity, and ferromagnetism. Monolayers that contain indium, monolayers that contain tin, and monolayers that contain cobalt are deposited onto a substrate and subsequently processed to form cobalt-doped indium-tin oxide. Devices that include oxide structures formed with these methods should have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: February 21, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8115243
    Abstract: A vertical transistor having an annular transistor body surrounding a vertical pillar, which can be made from oxide. The transistor body can be grown by a solid phase epitaxial growth process to avoid difficulties with forming sub-lithographic structures via etching processes. The body has ultra-thin dimensions and provides controlled short channel effects with reduced need for high doping levels. Buried data/bit lines are formed in an upper surface of a substrate from which the transistors extend. The transistor can be formed asymmetrically or offset with respect to the data/bit lines. The offset provides laterally asymmetric source regions of the transistors. Continuous conductive paths are provided in the data/bit lines which extend adjacent the source regions to provide better conductive characteristics of the data/bit lines, particularly for aggressively scaled processes.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8114763
    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 8102013
    Abstract: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOX) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the layer provides the functionality of a thinner silicon dioxide layer, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.
    Type: Grant
    Filed: March 10, 2009
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8101992
    Abstract: A memory array with staggered local data/bit lines extending generally in a first direction formed in an upper surface of a substrate and memory cell access transistors extending generally upward and aligned generally atop a corresponding local data/bit line. Selected columns of the memory cell access transistors are sacrificed to define local data/bit access transistors which are interconnected with overlying low resistance global data/bit lines. The global data/bit lines provide selectable low resistance paths between memory cells and sense amplifiers. The sacrificed memory cell access transistors and staggered local data/bit lines provide increased footprints for sense amplifiers to facilitate increased circuit integration.
    Type: Grant
    Filed: November 19, 2010
    Date of Patent: January 24, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20120015488
    Abstract: A dielectric such as a gate oxide and method of fabricating a gate oxide that produces a more reliable and thinner equivalent oxide thickness than conventional SiO2 gate oxides are provided. Gate oxides formed from elements such as zirconium are thermodynamically stable such that the gate oxides formed will have minimal reactions with a silicon substrate or other structures during any later high temperature processing stages. The process shown is performed at lower temperatures than the prior art, which further inhibits reactions with the silicon substrate or other structures. Using a thermal evaporation technique to deposit the layer to be oxidized, the underlying substrate surface smoothness is preserved, thus providing improved and more consistent electrical properties in the resulting gate oxide.
    Type: Application
    Filed: September 26, 2011
    Publication date: January 19, 2012
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8093638
    Abstract: Electronic systems and methods of forming the electronic systems include a gate dielectric having multiple lanthanide oxide layers. Such electronic systems may be used in a variety of electronic system applications. A dielectric film having a layer of a lanthanide oxide and a layer of another lanthanide oxide provides a reliable gate dielectric with an equivalent oxide thickness thinner than attainable using SiO2.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: January 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8093666
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by atomic layer deposition.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: January 10, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8084808
    Abstract: Electronic apparatus and systems include structures having a dielectric layer containing a zirconium silicon oxide film. A zirconium silicon oxide film may be disposed in an integrated circuit, as well as in a variety of other electronic devices. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8084370
    Abstract: Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Publication number: 20110308072
    Abstract: Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.
    Type: Application
    Filed: August 26, 2011
    Publication date: December 22, 2011
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8076249
    Abstract: A dielectric containing a titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8076727
    Abstract: Methods of forming transparent conducting oxides and devices formed by these methods are shown. Monolayers that contain zinc and monolayers that contain magnesium are deposited onto a substrate and subsequently processed to form magnesium-doped zinc oxide. The resulting transparent conducing oxide includes properties such as an amorphous or nanocrystalline microstructure. Devices that include transparent conducing oxides formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8076200
    Abstract: A nonvolatile read-only memory having a thin nitrided tunnel insulator surface with a charge blocking insulator over the nitrided surface is presented. The tunnel insulator may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. The dielectric structure may be formed by nitridation of a surface of a tunnel insulator using ammonia and deposition of a blocking insulator having a larger band gap than the tunnel insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 8076714
    Abstract: A memory cell transistor includes a high dielectric constant tunnel insulator, a metal floating gate, and a high dielectric constant inter-gate insulator comprising a metal oxide formed over a substrate. The tunnel insulator and inter-gate insulator have dielectric constants that are greater than silicon dioxide. Each memory cell has a plurality of doped source/drain regions in a substrate. A pair of transistors in a row are separated by an oxide isolation region comprising a low dielectric constant oxide material. A control gate is formed over the inter-gate insulator.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: December 13, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20110300701
    Abstract: Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.
    Type: Application
    Filed: August 19, 2011
    Publication date: December 8, 2011
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20110298028
    Abstract: Embodiments of a dielectric layer containing a hafnium tantalum titanium oxide film structured as one or more monolayers include the dielectric layer disposed in an integrated circuit. Embodiments of methods of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. An embodiment may include forming hafnium tantalum titanium oxide film using a monolayer or partial monolayer sequencing process such as atomic layer deposition.
    Type: Application
    Filed: August 12, 2011
    Publication date: December 8, 2011
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8071476
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a cobalt titanium oxide film on a substrate for use in a variety of electronic systems. The cobalt titanium oxide film may be structured as one or more monolayers. The cobalt titanium oxide film may be formed by atomic layer deposition.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: December 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8071443
    Abstract: Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: December 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes