Patents by Inventor Leonard Forbes

Leonard Forbes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170025467
    Abstract: Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region.
    Type: Application
    Filed: October 6, 2016
    Publication date: January 26, 2017
    Inventors: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Drake Miller, Chintamani Palsule, Leonard Forbes
  • Patent number: 9553122
    Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: January 24, 2017
    Assignee: INTELLECTUAL VENTURES II LLC
    Inventors: Jaroslav Hynecek, Leonard Forbes, Homayoon Haddad, Thomas Joy
  • Patent number: 9553177
    Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: January 24, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
  • Patent number: 9502256
    Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: November 22, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 9496308
    Abstract: Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: November 15, 2016
    Assignee: SiOnyx, LLC
    Inventors: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Drake Miller, Chintamani Palsule, Leonard Forbes
  • Publication number: 20160254270
    Abstract: A first conductive region having a second conductivity type is formed in a first semiconductor over a first dielectric isolation region and having a first conductivity type. A second semiconductor having the first conductivity type is formed over the first conductive region and the first semiconductor. Isolation structures are formed extending through the second semiconductor and the first semiconductor to the first dielectric isolation region, thereby defining a first well of the second semiconductor contained within the isolation structures and a second well of the first conductive region contained within the isolation structures. A charge-storage node is formed over the first well. Source/drain regions having the second conductivity type are formed in the first well adjacent the charge-storage node. A control gate is formed over the charge-storage node. A first contact is formed to the first well. A second contact is formed to the second well through the first well.
    Type: Application
    Filed: May 12, 2016
    Publication date: September 1, 2016
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Badih El-Kareh, Leonard Forbes
  • Publication number: 20160218236
    Abstract: An avalanche photodiode device operated in Geiger-mode, the device comprising a P-N junction formed on a substrate with a first semiconductor region and a second semiconductor region with an anode and cathode. The device further comprising a third semiconductor region, the third semiconductor region in physical contact with the second region, not in physical contact with the first region, and being the same semiconductor-type as the first semiconductor region. Additionally comprising a diode on the second semiconductor region and having a turn-on voltage than the P-N junction.
    Type: Application
    Filed: January 27, 2016
    Publication date: July 28, 2016
    Applicant: Voxtel, Inc.
    Inventors: Vinit DHULLA, Drake Miller, Leonard Forbes
  • Patent number: 9379241
    Abstract: In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: June 28, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Arup Bhattacharyya, Leonard Forbes, Paul A. Farrar
  • Patent number: 9361981
    Abstract: Methods of programming and forming memory devices. Methods of programming include biasing a control gate of a selected memory cell of the memory device to a first voltage, the control gate being over a first conductive region having a first conductivity type and the first conductive region being over a second conductive region having a second conductivity type different than the first conductivity type; biasing the second conductive region to a second voltage to forward bias the junction from the second conductive region to the first conductive region; and injecting electrons into a charge-storage node of the selected memory cell from the second conductive region. The first conductive region and the second conductive region are contained within a dielectric isolation structure in which at least the selected memory cell is contained.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: June 7, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Badih El-Kareh, Leonard Forbes
  • Patent number: 9356112
    Abstract: A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: May 31, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Publication number: 20160118259
    Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.
    Type: Application
    Filed: January 7, 2016
    Publication date: April 28, 2016
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20160071900
    Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 10, 2016
    Inventors: Jaroslav Hynecek, Leonard Forbes, Homayoon Haddad, Thomas Joy
  • Patent number: 9281065
    Abstract: Technologies are generally described for low-power nonvolatile memory cells configured with select gates. A nonvolatile memory cell may have a transistor body, a select gate and a floating gate both coupled to the body, and a control gate coupled to the floating gate. Charge stored on the floating gate may indicate the data stored on the memory cell, and the control gate may be configured to adjust the charge stored on the floating gate. The select gate may be used to adjust the state of the transistor body to facilitate the adjustment of charge on the floating gate, and may also be used to render the memory cell unresponsive to the control gate.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 8, 2016
    Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
    Inventor: Leonard Forbes
  • Publication number: 20160042793
    Abstract: Technologies are generally described for low-power nonvolatile memory cells configured with select gates. A nonvolatile memory cell may have a transistor body, a select gate and a floating gate both coupled to the body, and a control gate coupled to the floating gate. Charge stored on the floating gate may indicate the data stored on the memory cell, and the control gate may be configured to adjust the charge stored on the floating gate. The select gate may be used to adjust the state of the transistor body to facilitate the adjustment of charge on the floating gate, and may also be used to render the memory cell unresponsive to the control gate.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 11, 2016
    Inventor: Leonard Forbes
  • Patent number: 9252281
    Abstract: A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: February 2, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20160020322
    Abstract: In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.
    Type: Application
    Filed: September 29, 2015
    Publication date: January 21, 2016
    Inventors: Arup Bhattacharyya, Leonard Forbes, Paul A. Farrar
  • Patent number: 9236245
    Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: January 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 9231047
    Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: January 5, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes, Arup Bhattacharyya
  • Publication number: 20150380240
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 9202686
    Abstract: Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: December 1, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes