Patents by Inventor Leonard Forbes

Leonard Forbes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150325579
    Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Inventor: Leonard Forbes
  • Publication number: 20150287815
    Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.
    Type: Application
    Filed: June 18, 2015
    Publication date: October 8, 2015
    Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
  • Publication number: 20150270306
    Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 24, 2015
    Applicant: SiOnyx, Inc.
    Inventors: Homayoon Haddad, Jutao Jiang, Jeffrey McKee, Drake Miller, Leonard Forbes, Chintamani Palsule
  • Publication number: 20150262643
    Abstract: A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the semiconductor substrate and a body region and a second source/drain region are formed within the semiconductor pillar. A first gate is coupled to a first side of the semiconductor pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.
    Type: Application
    Filed: May 29, 2015
    Publication date: September 17, 2015
    Inventor: Leonard Forbes
  • Patent number: 9129961
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a gallium lanthanide oxide film for use in a variety of electronic systems. The gallium lanthanide oxide film may be structured as one or more monolayers. The gallium lanthanide oxide film may be formed using atomic layer deposition.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: September 8, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 9087730
    Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: July 21, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20150194299
    Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.
    Type: Application
    Filed: March 20, 2015
    Publication date: July 9, 2015
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 9076867
    Abstract: The present invention includes methods for stressing transistor channels of semiconductor device structures. Such methods include the formation of so-called near-surface “nanocavities” adjacent to the source/drain regions, forming extensions of the source/drain regions adjacent to and including the nanocavities, and implanting matter of a type that will expand or contract the volume of the nanocavities, depending respectively upon whether compressive strain is desirable in transistor channels between the nanocavities, as in PMOS field effect transistors, or tensile strain is wanted in transistor channels, as in NMOS field effect transistors, to enhance carrier mobility and transistor speed. Semiconductor device structures and semiconductor devices including these features are also disclosed.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Arup Bhattacharyya, Leonard Forbes, Paul A. Farrar
  • Patent number: 9076835
    Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Badih El-Kareh, Leonard Forbes, Kie Y. Ahn
  • Patent number: 9076662
    Abstract: Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: July 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Badih El-Kareh, Leonard Forbes
  • Patent number: 9064866
    Abstract: A metal oxide semiconductor (MOS) structure having a high dielectric constant gate insulator layer containing gold (Au) nano-particles is presented with methods for forming the layer with high step coverage of underlying topography, high surface smoothness, and uniform thickness. The transistor may form part of a logic device, a memory device, a persistent memory device, a capacitor, as well as other devices and systems. The insulator layer may be formed using atomic layer deposition (ALD) to reduce the overall device thermal exposure. The insulator layer may be formed of a metal oxide, a metal oxycarbide, a semiconductor oxide, or semiconductor oxide oxycarbide, and the gold nano-particles in insulator layer increase the work function of the insulator layer and affect the tunneling current and the threshold voltage of the transistor.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: June 23, 2015
    Assignee: Micro Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20150171165
    Abstract: According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. The oriented semiconductor layer is bonded to the substrate to strain the semiconductor layer. Various embodiments provide a tensile strain, and various embodiments provide a compressive strain. Other aspects and embodiments are provided herein.
    Type: Application
    Filed: February 23, 2015
    Publication date: June 18, 2015
    Inventor: Leonard Forbes
  • Patent number: 9048337
    Abstract: A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the semiconductor substrate and a body region and a second source/drain region are formed within the semiconductor pillar. A first gate is coupled to a first side of the semiconductor pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: June 2, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8993455
    Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 31, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8962447
    Abstract: According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. The oriented semiconductor layer is bonded to the substrate to strain the semiconductor layer. Various embodiments provide a tensile strain, and various embodiments provide a compressive strain. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: February 24, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8951880
    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Publication number: 20150035043
    Abstract: A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Publication number: 20150035119
    Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Inventors: Kie Y. Ahn, Leonard Forbes, Arup Bhattacharyya
  • Patent number: 8933449
    Abstract: Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8907486
    Abstract: A gate containing ruthenium for a dielectric having an oxide containing a lanthanide and a method of fabricating such a combination gate and dielectric produce a reliable structure for use in a variety of electronic devices. A ruthenium or a conductive ruthenium oxide gate may be formed on a lanthanide oxide. A ruthenium-based gate on a lanthanide oxide provides a gate structure that can effectively prevent a reaction between the gate and the lanthanide oxide.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes