Patents by Inventor Leonard Forbes

Leonard Forbes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8895442
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include cobalt titanium oxide on a substrate for use in a variety of electronic systems. The cobalt titanium oxide may be structured as one or more monolayers. The cobalt titanium oxide may be formed by a monolayer by monolayer sequencing process such as atomic layer deposition.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: November 25, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20140327065
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.
    Type: Application
    Filed: July 18, 2014
    Publication date: November 6, 2014
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20140322923
    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.
    Type: Application
    Filed: July 3, 2014
    Publication date: October 30, 2014
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 8865507
    Abstract: Semiconductor devices having three dimensional (3D) architectures and methods form making such devices are provided. In one aspect, for example, a method for making a semiconductor device can include forming a device layer on a front side of a semiconductor layer that is substantially defect free, bonding a carrier substrate to the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a smart substrate to the processed surface. In some aspects, the method can also include removing the carrier substrate from the semiconductor layer to expose the device layer.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: October 21, 2014
    Assignee: SiOnyx, Inc.
    Inventors: Homayoon Haddad, Leonard Forbes
  • Patent number: 8866210
    Abstract: A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: October 21, 2014
    Assignee: Micro Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 8865559
    Abstract: Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: October 21, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes, Arup Bhattacharyya
  • Publication number: 20140306307
    Abstract: The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy.
    Type: Application
    Filed: February 6, 2014
    Publication date: October 16, 2014
    Inventor: Leonard Forbes
  • Publication number: 20140307059
    Abstract: Stacked imager devices that can determine distance and generate three dimensional representations of a subject and associated methods are provided. In one aspect, an imaging system can include a first imager array having a first light incident surface and a second imager array having a second light incident surface. The second imager array can be coupled to the first imager array at a surface that is opposite the first light incident surface, with the second light incident surface being oriented toward the first imager array and at least substantially uniformly spaced. The system can also include a system lens positioned to direct incident light along an optical pathway onto the first light incident surface. The first imager array is operable to detect a first portion of the light passing along the optical pathway and to pass through a second portion of the light, where the second imager array is operable to detect at least a part of the second portion of light.
    Type: Application
    Filed: March 12, 2014
    Publication date: October 16, 2014
    Inventors: Homayoon Haddad, Chen Feng, Leonard Forbes
  • Patent number: 8847334
    Abstract: Methods of forming dielectric structures are shown. Methods of forming dielectric structures are shown that include lutetium oxide and lanthanum aluminum oxide crystals embedded within the lutetium oxide. Specific methods shown include monolayer deposition which yields process improvements such as chemistry control, step coverage, crystallinity/microstructure control.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20140264555
    Abstract: A monolayer or partial monolayer sequencing processing, such as atomic layer deposition (ALD), can be used to form a semiconductor structure of a silicon film on a germanium substrate. Such structures may be useful in high performance electronic devices. A structure may be formed by deposition of a thin silicon layer on a germanium substrate surface, forming a hafnium oxide dielectric layer, and forming a tantalum nitride electrode. The properties of the dielectric may be varied by replacing the hafnium oxide with another dielectric such as zirconium oxide or titanium oxide.
    Type: Application
    Filed: May 28, 2014
    Publication date: September 18, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20140246651
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallise the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallised semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Application
    Filed: May 13, 2014
    Publication date: September 4, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8823006
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin is formed from a crystalline substrate. A first source/drain region is formed in the substrate beneath the fin. A surrounding gate insulator is formed around the fin. A surrounding gate is formed around the fin and separated from the fin by the surrounding gate insulator. A second source/drain region is formed in a top portion of the fin. Various embodiments etch a hole in a layer over the substrate, form sidewall spacers in the hole, form a fin pattern from the sidewall spacers, and etch into the crystalline substrate to form the fin from the substrate using a mask corresponding to the fin pattern. Other aspects are provided herein.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 2, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8803229
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc
    Inventor: Leonard Forbes
  • Patent number: 8786006
    Abstract: A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the composition of the gate insulator is closer to silicon carbide near the substrate, the electron barrier for hot electron injection will be lower. If the gate insulator is closer to the silicon carbide near the floating gate, the tunnel barrier can be lower at the floating gate.
    Type: Grant
    Filed: August 27, 2012
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn
  • Patent number: 8785312
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include HfSiON for use in a variety of electronic systems. In various embodiments, conductive material is coupled to a dielectric containing HfSiON, where such conductive material may include one or more monolayers of titanium nitride, tantalum, or combinations of titanium nitride and tantalum.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 22, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20140197509
    Abstract: Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and a passivation region positioned between the textured region and the at least one junction. The passivation region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.
    Type: Application
    Filed: February 19, 2013
    Publication date: July 17, 2014
    Applicant: SiOnyx, Inc.
    Inventors: Homayoon Haddad, Jeffrey McKee, Jutao Jiang, Drake Miller, Chintamani Palsule, Leonard Forbes
  • Patent number: 8772851
    Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 8772050
    Abstract: The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide, produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. In various embodiments, structures can be formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. The properties of the dielectric may be tuned by adjusting the percentage of zirconium to titanium to optimize properties such as a dielectric constant, Curie point, film polarization, ferroelectric property and a desired relaxor response.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8765616
    Abstract: Dielectric layers containing a zirconium-doped tantalum oxide layer, where the zirconium-doped tantalum oxide layer can be formed of one or more monolayers of tantalum oxide doped with zirconium, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 1, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8759170
    Abstract: Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: June 24, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya